1 /*
2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <errno.h>
11
12 #include <bl31/bl31.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/dcc.h>
16 #include <drivers/arm/pl011.h>
17 #include <drivers/console.h>
18 #include <lib/cpus/cpu_ops.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables_v2.h>
21 #include <plat/common/platform.h>
22 #include <plat_arm.h>
23 #include <plat_console.h>
24
25 #include <custom_svc.h>
26 #include <def.h>
27 #include <plat_fdt.h>
28 #include <plat_private.h>
29 #include <plat_startup.h>
30 #if TRANSFER_LIST
31 #include <plat_xfer_list.h>
32 #endif
33 #include <pm_api_sys.h>
34 #include <pm_client.h>
35
36 #include <plat_ocm_coherency.h>
37
38 static entry_point_info_t bl32_image_ep_info;
39 static entry_point_info_t bl33_image_ep_info;
40
41 /*
42 * Return a pointer to the 'entry_point_info' structure of the next image for
43 * the security state specified. BL33 corresponds to the non-secure image type
44 * while BL32 corresponds to the secure image type. A NULL pointer is returned
45 * if the image does not exist.
46 */
bl31_plat_get_next_image_ep_info(uint32_t type)47 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
48 {
49 assert(sec_state_is_valid(type));
50
51 if (type == NON_SECURE) {
52 return &bl33_image_ep_info;
53 }
54
55 return &bl32_image_ep_info;
56 }
57
58 /*
59 * Set the build time defaults,if we can't find any config data.
60 */
bl31_set_default_config(void)61 static inline void bl31_set_default_config(void)
62 {
63 bl32_image_ep_info.pc = BL32_BASE;
64 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
65 #if defined(SPD_opteed)
66 #if (TRANSFER_LIST == 0)
67 /* NS dtb addr passed to optee_os */
68 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
69 #endif
70 #endif
71
72 #if defined(SPD_spmd)
73 bl32_image_ep_info.args.arg2 = XILINX_OF_BOARD_DTB_ADDR;
74 bl32_image_ep_info.args.arg0 = SPMC_MANIFEST_DTB_ADDR;
75 #endif
76
77 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
78 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
79 DISABLE_ALL_EXCEPTIONS);
80 }
81
82 /*
83 * Perform any BL31 specific platform actions. Here is an opportunity to copy
84 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
85 * are lost (potentially). This needs to be done before the MMU is initialized
86 * so that the memory layout can be used while creating page tables.
87 */
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)88 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
89 u_register_t arg2, u_register_t arg3)
90 {
91 (void)arg0;
92 (void)arg1;
93 (void)arg2;
94 (void)arg3;
95 uint32_t uart_clock;
96 #if (TRANSFER_LIST == 1)
97 int32_t rc;
98 bool tl_status = false;
99 #endif
100
101 board_detection();
102
103 /* FIXME */
104 switch (platform_id) {
105 case SPP:
106 switch (platform_version) {
107 case SPP_PSXC_MMI_V2_0:
108 cpu_clock = 770000;
109 break;
110 case SPP_PSXC_MMI_V3_0:
111 cpu_clock = 908000;
112 break;
113 default:
114 panic();
115 }
116 break;
117 case SPP_MMD:
118 switch (platform_version) {
119 case SPP_PSXC_ISP_AIE_V2_0:
120 case SPP_PSXC_MMD_AIE_FRZ_EA:
121 case SPP_PSXC_MMD_AIE_V3_0:
122 cpu_clock = 760000;
123 break;
124 default:
125 panic();
126 }
127 break;
128 case EMU:
129 case EMU_MMD:
130 cpu_clock = 112203;
131 break;
132 case QEMU:
133 case SILICON:
134 cpu_clock = 100000000;
135 break;
136 default:
137 panic();
138 }
139 #if (TRANSFER_LIST == 1)
140 tl_status = populate_data_from_xfer_list();
141 if (tl_status != true) {
142 WARN("Invalid transfer list\n");
143 }
144 #endif
145
146 uart_clock = get_uart_clk();
147
148 /* Initialize the platform config for future decision making */
149 config_setup();
150
151 setup_console();
152
153 if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) {
154 NOTICE("OCM coherency check not supported\n");
155 }
156
157 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n",
158 board_name_decode(),
159 (platform_version >> 1), platform_version % 10U,
160 (rtlversion >> 1), rtlversion % 10U,
161 (psversion >> 1), psversion % 10U,
162 (pmcversion >> 1), pmcversion % 10U);
163
164 /*
165 * Do initial security configuration to allow DRAM/device access. On
166 * Base only DRAM security is programmable (via TrustZone), but
167 * other platforms might have more programmable security devices
168 * present.
169 */
170
171 /* Populate common information for BL32 and BL33 */
172 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
173 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
174 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
175 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
176
177 #if (TRANSFER_LIST == 1)
178 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info);
179 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) {
180 NOTICE("BL31: TL not found, using default config\n");
181 bl31_set_default_config();
182 }
183 #else
184 bl31_set_default_config();
185 #endif
186
187 long rev_var = cpu_get_rev_var();
188
189 INFO("CPU Revision = 0x%lx\n", rev_var);
190 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock);
191 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE);
192 #if (defined(SPD_tspd) || defined(SPD_opteed))
193 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
194 #endif /* SPD_tspd || SPD_opteed */
195 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
196
197 custom_early_setup();
198
199 }
200
201 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
202
request_intr_type_el3(uint32_t id,interrupt_type_handler_t handler)203 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
204 {
205 static uint32_t index;
206 uint32_t i;
207 int32_t ret = 0;
208
209 /* Validate 'handler' and 'id' parameters */
210 if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
211 ret = -EINVAL;
212 goto exit_label;
213 }
214
215 /* Check if a handler has already been registered */
216 for (i = 0; i < index; i++) {
217 if (id == type_el3_interrupt_table[i].id) {
218 ret = -EALREADY;
219 goto exit_label;
220 }
221 }
222
223 type_el3_interrupt_table[index].id = id;
224 type_el3_interrupt_table[index].handler = handler;
225
226 index++;
227
228 exit_label:
229 return ret;
230 }
231
232 #if defined(SPD_none) || defined(SPD_opteed)
rdo_el3_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)233 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
234 void *handle, void *cookie)
235 {
236 (void)id;
237 uint32_t intr_id;
238 uint32_t i;
239 interrupt_type_handler_t handler = NULL;
240
241 intr_id = plat_ic_get_pending_interrupt_id();
242
243 for (i = 0; i < MAX_INTR_EL3; i++) {
244 if (intr_id == type_el3_interrupt_table[i].id) {
245 handler = type_el3_interrupt_table[i].handler;
246 }
247 }
248
249 if (handler != NULL) {
250 (void)handler(intr_id, flags, handle, cookie);
251 }
252
253 return 0;
254 }
255 #endif
256
257 #if defined(SPD_spmd)
plat_spmd_handle_group0_interrupt(uint32_t intid)258 int plat_spmd_handle_group0_interrupt(uint32_t intid)
259 {
260 uint32_t i;
261 interrupt_type_handler_t handler = NULL;
262
263 for (i = 0; i < MAX_INTR_EL3; i++) {
264 if (intid == type_el3_interrupt_table[i].id) {
265 handler = type_el3_interrupt_table[i].handler;
266 }
267 }
268
269 if (handler != NULL) {
270 /* TODO: Review handler logic and add error handling if needed */
271 (void)handler(intid, 0, NULL, NULL);
272 }
273
274 return 0;
275 }
276 #endif
277
bl31_platform_setup(void)278 void bl31_platform_setup(void)
279 {
280 prepare_dtb();
281
282 /* Initialize the gic cpu and distributor interfaces */
283 plat_gic_driver_init();
284 plat_gic_init();
285 }
286
bl31_plat_runtime_setup(void)287 void bl31_plat_runtime_setup(void)
288 {
289 uint32_t rre_ret = 0;
290 #if defined(SPD_none) || defined(SPD_opteed)
291 uint32_t flags = 0;
292 int32_t rc;
293
294 set_interrupt_rm_flag(flags, NON_SECURE);
295 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
296 rdo_el3_interrupt_handler, flags);
297 if (rc != 0) {
298 panic();
299 }
300 #endif
301
302 /* Instead of calling for each time fill in structure early. */
303 rre_ret = retrieve_reserved_entries();
304
305 if (rre_ret != 0) {
306 INFO("Runtime FDT reserve node retreival failed");
307 }
308
309 custom_runtime_setup();
310
311 console_switch_state(CONSOLE_FLAG_RUNTIME);
312 }
313
314 /*
315 * Perform the very early platform specific architectural setup here.
316 */
bl31_plat_arch_setup(void)317 void bl31_plat_arch_setup(void)
318 {
319 const mmap_region_t bl_regions[] = {
320 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
321 MT_MEMORY | MT_RW | MT_SECURE),
322 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
323 MT_CODE | MT_SECURE),
324 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
325 MT_RO_DATA | MT_SECURE),
326 {0}
327 };
328
329 custom_mmap_add();
330
331 setup_page_tables(bl_regions, plat_get_mmap());
332 enable_mmu(0);
333 }
334