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Searched defs:sunxi_mctl_phy_reg (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h163 struct sunxi_mctl_phy_reg { struct
164 u8 res0[0x04]; /* 0x00 */
165 u32 pir; /* 0x04 */
166 u32 pgcr0; /* 0x08 phy general configuration register */
167 u32 pgcr1; /* 0x0c phy general configuration register */
168 u32 pgsr0; /* 0x10 */
169 u32 pgsr1; /* 0x14 */
170 u32 dllgcr; /* 0x18 */
171 u32 ptr0; /* 0x1c */
172 u32 ptr1; /* 0x20 */
[all …]
H A Ddram_sun6i.h157 struct sunxi_mctl_phy_reg { struct
158 u8 res0[0x04]; /* 0x00 */
159 u32 pir; /* 0x04 */
160 u32 pgcr; /* 0x08 phy general configuration register */
161 u32 pgsr; /* 0x0c */
162 u32 dllgcr; /* 0x10 */
163 u32 acdllcr; /* 0x14 */
164 u32 ptr0; /* 0x18 */
165 u32 ptr1; /* 0x1c */
166 u32 ptr2; /* 0x20 */
[all …]
H A Ddram_sun9i.h93 struct sunxi_mctl_phy_reg { struct
94 u8 res0[0x04]; /* 0x00 revision id ??? */
95 u32 pir; /* 0x04 PHY initialisation register */
96 u32 pgcr[4]; /* 0x08 PHY general configuration register */
97 u32 pgsr[2]; /* 0x18 PHY general status register */
98 u32 pllcr; /* 0x20 PLL control register */
99 u32 ptr[5]; /* 0x24 PHY timing register */
100 u32 acmdlr; /* 0x38 AC master delay line register */
101 u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */
102 u32 acbdlr[10]; /* 0x40 AC bit delay line register */
[all …]