1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2020 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 /* Target CPU versions for D. */ 30 #define TARGET_D_CPU_VERSIONS aarch64_d_target_versions 31 32 33 34 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 35 36 /* Target machine storage layout. */ 37 38 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 39 if (GET_MODE_CLASS (MODE) == MODE_INT \ 40 && GET_MODE_SIZE (MODE) < 4) \ 41 { \ 42 if (MODE == QImode || MODE == HImode) \ 43 { \ 44 MODE = SImode; \ 45 } \ 46 } 47 48 /* Bits are always numbered from the LSBit. */ 49 #define BITS_BIG_ENDIAN 0 50 51 /* Big/little-endian flavour. */ 52 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 53 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 54 55 /* AdvSIMD is supported in the default configuration, unless disabled by 56 -mgeneral-regs-only or by the +nosimd extension. */ 57 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 58 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 59 60 #define UNITS_PER_WORD 8 61 62 #define UNITS_PER_VREG 16 63 64 #define PARM_BOUNDARY 64 65 66 #define STACK_BOUNDARY 128 67 68 #define FUNCTION_BOUNDARY 32 69 70 #define EMPTY_FIELD_BOUNDARY 32 71 72 #define BIGGEST_ALIGNMENT 128 73 74 #define SHORT_TYPE_SIZE 16 75 76 #define INT_TYPE_SIZE 32 77 78 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 79 80 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 81 82 #define LONG_LONG_TYPE_SIZE 64 83 84 #define FLOAT_TYPE_SIZE 32 85 86 #define DOUBLE_TYPE_SIZE 64 87 88 #define LONG_DOUBLE_TYPE_SIZE 128 89 90 /* This value is the amount of bytes a caller is allowed to drop the stack 91 before probing has to be done for stack clash protection. */ 92 #define STACK_CLASH_CALLER_GUARD 1024 93 94 /* This value represents the minimum amount of bytes we expect the function's 95 outgoing arguments to be when stack-clash is enabled. */ 96 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 97 98 /* This value controls how many pages we manually unroll the loop for when 99 generating stack clash probes. */ 100 #define STACK_CLASH_MAX_UNROLL_PAGES 4 101 102 /* The architecture reserves all bits of the address for hardware use, 103 so the vbit must go into the delta field of pointers to member 104 functions. This is the same config as that in the AArch32 105 port. */ 106 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 107 108 109 /* Emit calls to libgcc helpers for atomic operations for runtime detection 110 of LSE instructions. */ 111 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics) 112 113 /* Align definitions of arrays, unions and structures so that 114 initializations and copies can be made more efficient. This is not 115 ABI-changing, so it only affects places where we can see the 116 definition. Increasing the alignment tends to introduce padding, 117 so don't do this when optimizing for size/conserving stack space. */ 118 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 119 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 120 && (TREE_CODE (EXP) == ARRAY_TYPE \ 121 || TREE_CODE (EXP) == UNION_TYPE \ 122 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 123 124 /* Align global data. */ 125 #define DATA_ALIGNMENT(EXP, ALIGN) \ 126 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) 127 128 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 129 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 130 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) 131 132 #define STRUCTURE_SIZE_BOUNDARY 8 133 134 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ 135 #define MALLOC_ABI_ALIGNMENT 128 136 137 /* Defined by the ABI */ 138 #define WCHAR_TYPE "unsigned int" 139 #define WCHAR_TYPE_SIZE 32 140 141 /* Using long long breaks -ansi and -std=c90, so these will need to be 142 made conditional for an LLP64 ABI. */ 143 144 #define SIZE_TYPE "long unsigned int" 145 146 #define PTRDIFF_TYPE "long int" 147 148 #define PCC_BITFIELD_TYPE_MATTERS 1 149 150 /* Major revision number of the ARM Architecture implemented by the target. */ 151 extern unsigned aarch64_architecture_version; 152 153 /* Instruction tuning/selection flags. */ 154 155 /* Bit values used to identify processor capabilities. */ 156 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 157 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 158 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 159 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 160 /* ARMv8.1-A architecture extensions. */ 161 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 162 #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ 163 #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ 164 /* ARMv8.2-A architecture extensions. */ 165 #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ 166 #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ 167 #define AARCH64_FL_SVE (1 << 10) /* Has Scalable Vector Extensions. */ 168 /* ARMv8.3-A architecture extensions. */ 169 #define AARCH64_FL_V8_3 (1 << 11) /* Has ARMv8.3-A features. */ 170 #define AARCH64_FL_RCPC (1 << 12) /* Has support for RCpc model. */ 171 #define AARCH64_FL_DOTPROD (1 << 13) /* Has ARMv8.2-A Dot Product ins. */ 172 /* New flags to split crypto into aes and sha2. */ 173 #define AARCH64_FL_AES (1 << 14) /* Has Crypto AES. */ 174 #define AARCH64_FL_SHA2 (1 << 15) /* Has Crypto SHA2. */ 175 /* ARMv8.4-A architecture extensions. */ 176 #define AARCH64_FL_V8_4 (1 << 16) /* Has ARMv8.4-A features. */ 177 #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ 178 #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ 179 #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ 180 #define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ 181 182 /* Statistical Profiling extensions. */ 183 #define AARCH64_FL_PROFILE (1 << 21) 184 185 /* ARMv8.5-A architecture extensions. */ 186 #define AARCH64_FL_V8_5 (1 << 22) /* Has ARMv8.5-A features. */ 187 #define AARCH64_FL_RNG (1 << 23) /* ARMv8.5-A Random Number Insns. */ 188 #define AARCH64_FL_MEMTAG (1 << 24) /* ARMv8.5-A Memory Tagging 189 Extensions. */ 190 191 /* Speculation Barrier instruction supported. */ 192 #define AARCH64_FL_SB (1 << 25) 193 194 /* Speculative Store Bypass Safe instruction supported. */ 195 #define AARCH64_FL_SSBS (1 << 26) 196 197 /* Execution and Data Prediction Restriction instructions supported. */ 198 #define AARCH64_FL_PREDRES (1 << 27) 199 200 /* SVE2 instruction supported. */ 201 #define AARCH64_FL_SVE2 (1 << 28) 202 #define AARCH64_FL_SVE2_AES (1 << 29) 203 #define AARCH64_FL_SVE2_SM4 (1 << 30) 204 #define AARCH64_FL_SVE2_SHA3 (1ULL << 31) 205 #define AARCH64_FL_SVE2_BITPERM (1ULL << 32) 206 207 /* Transactional Memory Extension. */ 208 #define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ 209 210 /* Armv8.6-A architecture extensions. */ 211 #define AARCH64_FL_V8_6 (1ULL << 34) 212 213 /* 8-bit Integer Matrix Multiply (I8MM) extensions. */ 214 #define AARCH64_FL_I8MM (1ULL << 35) 215 216 /* Brain half-precision floating-point (BFloat16) Extension. */ 217 #define AARCH64_FL_BF16 (1ULL << 36) 218 219 /* 32-bit Floating-point Matrix Multiply (F32MM) extensions. */ 220 #define AARCH64_FL_F32MM (1ULL << 37) 221 222 /* 64-bit Floating-point Matrix Multiply (F64MM) extensions. */ 223 #define AARCH64_FL_F64MM (1ULL << 38) 224 225 /* Has FP and SIMD. */ 226 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 227 228 /* Has FP without SIMD. */ 229 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 230 231 /* Architecture flags that effect instruction selection. */ 232 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 233 #define AARCH64_FL_FOR_ARCH8_1 \ 234 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ 235 | AARCH64_FL_RDMA | AARCH64_FL_V8_1) 236 #define AARCH64_FL_FOR_ARCH8_2 \ 237 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) 238 #define AARCH64_FL_FOR_ARCH8_3 \ 239 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3) 240 #define AARCH64_FL_FOR_ARCH8_4 \ 241 (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ 242 | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4) 243 #define AARCH64_FL_FOR_ARCH8_5 \ 244 (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ 245 | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) 246 #define AARCH64_FL_FOR_ARCH8_6 \ 247 (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \ 248 | AARCH64_FL_I8MM | AARCH64_FL_BF16) 249 250 /* Macros to test ISA flags. */ 251 252 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 253 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 254 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 255 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 256 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 257 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) 258 #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) 259 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 260 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) 261 #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) 262 #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) 263 #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) 264 #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) 265 #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) 266 #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) 267 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) 268 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) 269 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) 270 #define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4) 271 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) 272 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) 273 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) 274 #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) 275 #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) 276 #define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5) 277 #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) 278 #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) 279 #define AARCH64_ISA_V8_6 (aarch64_isa_flags & AARCH64_FL_V8_6) 280 #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) 281 #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) 282 #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) 283 #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) 284 #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) 285 286 /* Crypto is an optional extension to AdvSIMD. */ 287 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 288 289 /* SHA2 is an optional extension to AdvSIMD. */ 290 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) 291 292 /* SHA3 is an optional extension to AdvSIMD. */ 293 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) 294 295 /* AES is an optional extension to AdvSIMD. */ 296 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) 297 298 /* SM is an optional extension to AdvSIMD. */ 299 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) 300 301 /* FP16FML is an optional extension to AdvSIMD. */ 302 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) 303 304 /* CRC instructions that can be enabled through +crc arch extension. */ 305 #define TARGET_CRC32 (AARCH64_ISA_CRC) 306 307 /* Atomic instructions that can be enabled through the +lse extension. */ 308 #define TARGET_LSE (AARCH64_ISA_LSE) 309 310 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 311 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) 312 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 313 314 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ 315 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) 316 317 /* SVE instructions, enabled through +sve. */ 318 #define TARGET_SVE (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SVE) 319 320 /* SVE2 instructions, enabled through +sve2. */ 321 #define TARGET_SVE2 (TARGET_SVE && AARCH64_ISA_SVE2) 322 323 /* SVE2 AES instructions, enabled through +sve2-aes. */ 324 #define TARGET_SVE2_AES (TARGET_SVE2 && AARCH64_ISA_SVE2_AES) 325 326 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ 327 #define TARGET_SVE2_BITPERM (TARGET_SVE2 && AARCH64_ISA_SVE2_BITPERM) 328 329 /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ 330 #define TARGET_SVE2_SHA3 (TARGET_SVE2 && AARCH64_ISA_SVE2_SHA3) 331 332 /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ 333 #define TARGET_SVE2_SM4 (TARGET_SVE2 && AARCH64_ISA_SVE2_SM4) 334 335 /* ARMv8.3-A features. */ 336 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) 337 338 /* Javascript conversion instruction from Armv8.3-a. */ 339 #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) 340 341 /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ 342 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) 343 344 /* Floating-point rounding instructions from Armv8.5-a. */ 345 #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT) 346 347 /* TME instructions are enabled. */ 348 #define TARGET_TME (AARCH64_ISA_TME) 349 350 /* Random number instructions from Armv8.5-a. */ 351 #define TARGET_RNG (AARCH64_ISA_RNG) 352 353 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ 354 #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG) 355 356 /* I8MM instructions are enabled through +i8mm. */ 357 #define TARGET_I8MM (AARCH64_ISA_I8MM) 358 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) 359 360 /* F32MM instructions are enabled through +f32mm. */ 361 #define TARGET_F32MM (AARCH64_ISA_F32MM) 362 #define TARGET_SVE_F32MM (TARGET_SVE && AARCH64_ISA_F32MM) 363 364 /* F64MM instructions are enabled through +f64mm. */ 365 #define TARGET_F64MM (AARCH64_ISA_F64MM) 366 #define TARGET_SVE_F64MM (TARGET_SVE && AARCH64_ISA_F64MM) 367 368 /* BF16 instructions are enabled through +bf16. */ 369 #define TARGET_BF16_FP (AARCH64_ISA_BF16) 370 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) 371 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) 372 373 /* Make sure this is always defined so we don't have to check for ifdefs 374 but rather use normal ifs. */ 375 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 376 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 377 #else 378 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 379 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 380 #endif 381 382 /* SB instruction is enabled through +sb. */ 383 #define TARGET_SB (AARCH64_ISA_SB) 384 385 /* Apply the workaround for Cortex-A53 erratum 835769. */ 386 #define TARGET_FIX_ERR_A53_835769 \ 387 ((aarch64_fix_a53_err835769 == 2) \ 388 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 389 390 /* Make sure this is always defined so we don't have to check for ifdefs 391 but rather use normal ifs. */ 392 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 393 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 394 #else 395 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 396 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 397 #endif 398 399 /* Apply the workaround for Cortex-A53 erratum 843419. */ 400 #define TARGET_FIX_ERR_A53_843419 \ 401 ((aarch64_fix_a53_err843419 == 2) \ 402 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 403 404 /* ARMv8.1-A Adv.SIMD support. */ 405 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 406 407 /* Standard register usage. */ 408 409 /* 31 64-bit general purpose registers R0-R30: 410 R30 LR (link register) 411 R29 FP (frame pointer) 412 R19-R28 Callee-saved registers 413 R18 The platform register; use as temporary register. 414 R17 IP1 The second intra-procedure-call temporary register 415 (can be used by call veneers and PLT code); otherwise use 416 as a temporary register 417 R16 IP0 The first intra-procedure-call temporary register (can 418 be used by call veneers and PLT code); otherwise use as a 419 temporary register 420 R9-R15 Temporary registers 421 R8 Structure value parameter / temporary register 422 R0-R7 Parameter/result registers 423 424 SP stack pointer, encoded as X/R31 where permitted. 425 ZR zero register, encoded as X/R31 elsewhere 426 427 32 x 128-bit floating-point/vector registers 428 V16-V31 Caller-saved (temporary) registers 429 V8-V15 Callee-saved registers 430 V0-V7 Parameter/result registers 431 432 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 433 significant bits. Unlike AArch32 S1 is not packed into D0, etc. 434 435 P0-P7 Predicate low registers: valid in all predicate contexts 436 P8-P15 Predicate high registers: used as scratch space 437 438 FFR First Fault Register, a fixed-use SVE predicate register 439 FFRT FFR token: a fake register used for modelling dependencies 440 441 VG Pseudo "vector granules" register 442 443 VG is the number of 64-bit elements in an SVE vector. We define 444 it as a hard register so that we can easily map it to the DWARF VG 445 register. GCC internally uses the poly_int variable aarch64_sve_vg 446 instead. */ 447 448 #define FIXED_REGISTERS \ 449 { \ 450 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 451 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 452 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 453 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 454 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 455 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 456 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 457 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 458 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 459 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ 460 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ 461 1, 1 /* FFR and FFRT */ \ 462 } 463 464 /* X30 is marked as caller-saved which is in line with regular function call 465 behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does 466 that for regular function calls and avoids it for sibcalls. X30 is 467 considered live for sibcalls; EPILOGUE_USES helps achieve that by returning 468 true but not until function epilogues have been generated. This ensures 469 that X30 is available for use in leaf functions if needed. */ 470 471 #define CALL_USED_REGISTERS \ 472 { \ 473 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 474 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 475 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 476 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 477 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 478 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 479 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 480 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 481 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 482 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ 483 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ 484 1, 1 /* FFR and FFRT */ \ 485 } 486 487 #define REGISTER_NAMES \ 488 { \ 489 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 490 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 491 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 492 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 493 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 494 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 495 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 496 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 497 "sfp", "ap", "cc", "vg", \ 498 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ 499 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ 500 "ffr", "ffrt" \ 501 } 502 503 /* Generate the register aliases for core register N */ 504 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 505 {"w" # N, R0_REGNUM + (N)} 506 507 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 508 {"d" # N, V0_REGNUM + (N)}, \ 509 {"s" # N, V0_REGNUM + (N)}, \ 510 {"h" # N, V0_REGNUM + (N)}, \ 511 {"b" # N, V0_REGNUM + (N)}, \ 512 {"z" # N, V0_REGNUM + (N)} 513 514 /* Provide aliases for all of the ISA defined register name forms. 515 These aliases are convenient for use in the clobber lists of inline 516 asm statements. */ 517 518 #define ADDITIONAL_REGISTER_NAMES \ 519 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 520 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 521 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 522 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 523 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 524 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 525 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 526 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 527 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 528 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 529 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 530 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 531 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 532 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 533 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 534 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 535 } 536 537 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) 538 539 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 540 the stack pointer does not matter. This is only true if the function 541 uses alloca. */ 542 #define EXIT_IGNORE_STACK (cfun->calls_alloca) 543 544 #define STATIC_CHAIN_REGNUM R18_REGNUM 545 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 546 #define FRAME_POINTER_REGNUM SFP_REGNUM 547 #define STACK_POINTER_REGNUM SP_REGNUM 548 #define ARG_POINTER_REGNUM AP_REGNUM 549 #define FIRST_PSEUDO_REGISTER (FFRT_REGNUM + 1) 550 551 /* The number of argument registers available for each class. */ 552 #define NUM_ARG_REGS 8 553 #define NUM_FP_ARG_REGS 8 554 #define NUM_PR_ARG_REGS 4 555 556 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 557 four members. */ 558 #define HA_MAX_NUM_FLDS 4 559 560 /* External dwarf register number scheme. These number are used to 561 identify registers in dwarf debug information, the values are 562 defined by the AArch64 ABI. The numbering scheme is independent of 563 GCC's internal register numbering scheme. */ 564 565 #define AARCH64_DWARF_R0 0 566 567 /* The number of R registers, note 31! not 32. */ 568 #define AARCH64_DWARF_NUMBER_R 31 569 570 #define AARCH64_DWARF_SP 31 571 #define AARCH64_DWARF_VG 46 572 #define AARCH64_DWARF_P0 48 573 #define AARCH64_DWARF_V0 64 574 575 /* The number of V registers. */ 576 #define AARCH64_DWARF_NUMBER_V 32 577 578 /* For signal frames we need to use an alternative return column. This 579 value must not correspond to a hard register and must be out of the 580 range of DWARF_FRAME_REGNUM(). */ 581 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 582 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 583 584 /* We add 1 extra frame register for use as the 585 DWARF_ALT_FRAME_RETURN_COLUMN. */ 586 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 587 588 589 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 590 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 591 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 592 as the default definition in dwarf2out.c. */ 593 #undef DWARF_FRAME_REGNUM 594 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 595 596 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 597 598 #define DWARF2_UNWIND_INFO 1 599 600 /* Use R0 through R3 to pass exception handling information. */ 601 #define EH_RETURN_DATA_REGNO(N) \ 602 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 603 604 /* Select a format to encode pointers in exception handling data. */ 605 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 606 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 607 608 /* Output the assembly strings we want to add to a function definition. */ 609 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 610 aarch64_declare_function_name (STR, NAME, DECL) 611 612 /* Output assembly strings for alias definition. */ 613 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ 614 aarch64_asm_output_alias (STR, DECL, TARGET) 615 616 /* Output assembly strings for undefined extern symbols. */ 617 #undef ASM_OUTPUT_EXTERNAL 618 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ 619 aarch64_asm_output_external (STR, DECL, NAME) 620 621 /* Output assembly strings after .cfi_startproc is emitted. */ 622 #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc 623 624 /* For EH returns X4 contains the stack adjustment. */ 625 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 626 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 627 628 /* Don't use __builtin_setjmp until we've defined it. */ 629 #undef DONT_USE_BUILTIN_SETJMP 630 #define DONT_USE_BUILTIN_SETJMP 1 631 632 #undef TARGET_COMPUTE_FRAME_LAYOUT 633 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame 634 635 /* Register in which the structure value is to be returned. */ 636 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 637 638 /* Non-zero if REGNO is part of the Core register set. 639 640 The rather unusual way of expressing this check is to avoid 641 warnings when building the compiler when R0_REGNUM is 0 and REGNO 642 is unsigned. */ 643 #define GP_REGNUM_P(REGNO) \ 644 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 645 646 /* Registers known to be preserved over a BL instruction. This consists of the 647 GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the 648 BL instruction itself, while the x16 and x17 registers may be used by 649 veneers which can be inserted by the linker. */ 650 #define STUB_REGNUM_P(REGNO) \ 651 (GP_REGNUM_P (REGNO) \ 652 && (REGNO) != R16_REGNUM \ 653 && (REGNO) != R17_REGNUM \ 654 && (REGNO) != R30_REGNUM) \ 655 656 #define FP_REGNUM_P(REGNO) \ 657 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 658 659 #define FP_LO_REGNUM_P(REGNO) \ 660 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 661 662 #define FP_LO8_REGNUM_P(REGNO) \ 663 (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) 664 665 #define PR_REGNUM_P(REGNO)\ 666 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) 667 668 #define PR_LO_REGNUM_P(REGNO)\ 669 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) 670 671 #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ 672 (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) 673 674 /* Register and constant classes. */ 675 676 enum reg_class 677 { 678 NO_REGS, 679 TAILCALL_ADDR_REGS, 680 STUB_REGS, 681 GENERAL_REGS, 682 STACK_REG, 683 POINTER_REGS, 684 FP_LO8_REGS, 685 FP_LO_REGS, 686 FP_REGS, 687 POINTER_AND_FP_REGS, 688 PR_LO_REGS, 689 PR_HI_REGS, 690 PR_REGS, 691 FFR_REGS, 692 PR_AND_FFR_REGS, 693 ALL_REGS, 694 LIM_REG_CLASSES /* Last */ 695 }; 696 697 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 698 699 #define REG_CLASS_NAMES \ 700 { \ 701 "NO_REGS", \ 702 "TAILCALL_ADDR_REGS", \ 703 "STUB_REGS", \ 704 "GENERAL_REGS", \ 705 "STACK_REG", \ 706 "POINTER_REGS", \ 707 "FP_LO8_REGS", \ 708 "FP_LO_REGS", \ 709 "FP_REGS", \ 710 "POINTER_AND_FP_REGS", \ 711 "PR_LO_REGS", \ 712 "PR_HI_REGS", \ 713 "PR_REGS", \ 714 "FFR_REGS", \ 715 "PR_AND_FFR_REGS", \ 716 "ALL_REGS" \ 717 } 718 719 #define REG_CLASS_CONTENTS \ 720 { \ 721 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 722 { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 723 { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ 724 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 725 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 726 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 727 { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ 728 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 729 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 730 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ 731 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ 732 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ 733 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ 734 { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \ 735 { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \ 736 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ 737 } 738 739 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 740 741 #define INDEX_REG_CLASS GENERAL_REGS 742 #define BASE_REG_CLASS POINTER_REGS 743 744 /* Register pairs used to eliminate unneeded registers that point into 745 the stack frame. */ 746 #define ELIMINABLE_REGS \ 747 { \ 748 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 749 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 750 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 751 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 752 } 753 754 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 755 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 756 757 /* CPU/ARCH option handling. */ 758 #include "config/aarch64/aarch64-opts.h" 759 760 enum target_cpus 761 { 762 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 763 TARGET_CPU_##INTERNAL_IDENT, 764 #include "aarch64-cores.def" 765 TARGET_CPU_generic 766 }; 767 768 /* If there is no CPU defined at configure, use generic as default. */ 769 #ifndef TARGET_CPU_DEFAULT 770 #define TARGET_CPU_DEFAULT \ 771 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 772 #endif 773 774 /* If inserting NOP before a mult-accumulate insn remember to adjust the 775 length so that conditional branching code is updated appropriately. */ 776 #define ADJUST_INSN_LENGTH(insn, length) \ 777 do \ 778 { \ 779 if (aarch64_madd_needs_nop (insn)) \ 780 length += 4; \ 781 } while (0) 782 783 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 784 aarch64_final_prescan_insn (INSN); \ 785 786 /* The processor for which instructions should be scheduled. */ 787 extern enum aarch64_processor aarch64_tune; 788 789 /* RTL generation support. */ 790 #define INIT_EXPANDERS aarch64_init_expanders () 791 792 793 /* Stack layout; function entry, exit and calling. */ 794 #define STACK_GROWS_DOWNWARD 1 795 796 #define FRAME_GROWS_DOWNWARD 1 797 798 #define ACCUMULATE_OUTGOING_ARGS 1 799 800 #define FIRST_PARM_OFFSET(FNDECL) 0 801 802 /* Fix for VFP */ 803 #define LIBCALL_VALUE(MODE) \ 804 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 805 806 #define DEFAULT_PCC_STRUCT_RETURN 0 807 808 #ifdef HAVE_POLY_INT_H 809 struct GTY (()) aarch64_frame 810 { 811 poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; 812 813 /* The number of extra stack bytes taken up by register varargs. 814 This area is allocated by the callee at the very top of the 815 frame. This value is rounded up to a multiple of 816 STACK_BOUNDARY. */ 817 HOST_WIDE_INT saved_varargs_size; 818 819 /* The size of the callee-save registers with a slot in REG_OFFSET. */ 820 poly_int64 saved_regs_size; 821 822 /* The size of the callee-save registers with a slot in REG_OFFSET that 823 are saved below the hard frame pointer. */ 824 poly_int64 below_hard_fp_saved_regs_size; 825 826 /* Offset from the base of the frame (incomming SP) to the 827 top of the locals area. This value is always a multiple of 828 STACK_BOUNDARY. */ 829 poly_int64 locals_offset; 830 831 /* Offset from the base of the frame (incomming SP) to the 832 hard_frame_pointer. This value is always a multiple of 833 STACK_BOUNDARY. */ 834 poly_int64 hard_fp_offset; 835 836 /* The size of the frame. This value is the offset from base of the 837 frame (incomming SP) to the stack_pointer. This value is always 838 a multiple of STACK_BOUNDARY. */ 839 poly_int64 frame_size; 840 841 /* The size of the initial stack adjustment before saving callee-saves. */ 842 poly_int64 initial_adjust; 843 844 /* The writeback value when pushing callee-save registers. 845 It is zero when no push is used. */ 846 HOST_WIDE_INT callee_adjust; 847 848 /* The offset from SP to the callee-save registers after initial_adjust. 849 It may be non-zero if no push is used (ie. callee_adjust == 0). */ 850 poly_int64 callee_offset; 851 852 /* The size of the stack adjustment before saving or after restoring 853 SVE registers. */ 854 poly_int64 sve_callee_adjust; 855 856 /* The size of the stack adjustment after saving callee-saves. */ 857 poly_int64 final_adjust; 858 859 /* Store FP,LR and setup a frame pointer. */ 860 bool emit_frame_chain; 861 862 unsigned wb_candidate1; 863 unsigned wb_candidate2; 864 865 /* Big-endian SVE frames need a spare predicate register in order 866 to save vector registers in the correct layout for unwinding. 867 This is the register they should use. */ 868 unsigned spare_pred_reg; 869 870 bool laid_out; 871 }; 872 873 typedef struct GTY (()) machine_function 874 { 875 struct aarch64_frame frame; 876 /* One entry for each hard register. */ 877 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 878 /* One entry for each general purpose register. */ 879 rtx call_via[SP_REGNUM]; 880 bool label_is_assembled; 881 } machine_function; 882 #endif 883 884 /* Which ABI to use. */ 885 enum aarch64_abi_type 886 { 887 AARCH64_ABI_LP64 = 0, 888 AARCH64_ABI_ILP32 = 1 889 }; 890 891 #ifndef AARCH64_ABI_DEFAULT 892 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 893 #endif 894 895 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 896 897 enum arm_pcs 898 { 899 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 900 ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ 901 ARM_PCS_SVE, /* For functions that pass or return 902 values in SVE registers. */ 903 ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ 904 ARM_PCS_UNKNOWN 905 }; 906 907 908 909 910 /* We can't use machine_mode inside a generator file because it 911 hasn't been created yet; we shouldn't be using any code that 912 needs the real definition though, so this ought to be safe. */ 913 #ifdef GENERATOR_FILE 914 #define MACHMODE int 915 #else 916 #include "insn-modes.h" 917 #define MACHMODE machine_mode 918 #endif 919 920 #ifndef USED_FOR_TARGET 921 /* AAPCS related state tracking. */ 922 typedef struct 923 { 924 enum arm_pcs pcs_variant; 925 int aapcs_arg_processed; /* No need to lay out this argument again. */ 926 int aapcs_ncrn; /* Next Core register number. */ 927 int aapcs_nextncrn; /* Next next core register number. */ 928 int aapcs_nvrn; /* Next Vector register number. */ 929 int aapcs_nextnvrn; /* Next Next Vector register number. */ 930 int aapcs_nprn; /* Next Predicate register number. */ 931 int aapcs_nextnprn; /* Next Next Predicate register number. */ 932 rtx aapcs_reg; /* Register assigned to this argument. This 933 is NULL_RTX if this parameter goes on 934 the stack. */ 935 MACHMODE aapcs_vfp_rmode; 936 int aapcs_stack_words; /* If the argument is passed on the stack, this 937 is the number of words needed, after rounding 938 up. Only meaningful when 939 aapcs_reg == NULL_RTX. */ 940 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 941 stack arg area so far. */ 942 bool silent_p; /* True if we should act silently, rather than 943 raise an error for invalid calls. */ 944 } CUMULATIVE_ARGS; 945 #endif 946 947 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 948 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 949 950 #define PAD_VARARGS_DOWN 0 951 952 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 953 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 954 955 #define FUNCTION_ARG_REGNO_P(REGNO) \ 956 aarch64_function_arg_regno_p(REGNO) 957 958 959 /* ISA Features. */ 960 961 /* Addressing modes, etc. */ 962 #define HAVE_POST_INCREMENT 1 963 #define HAVE_PRE_INCREMENT 1 964 #define HAVE_POST_DECREMENT 1 965 #define HAVE_PRE_DECREMENT 1 966 #define HAVE_POST_MODIFY_DISP 1 967 #define HAVE_PRE_MODIFY_DISP 1 968 969 #define MAX_REGS_PER_ADDRESS 2 970 971 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 972 973 #define REGNO_OK_FOR_BASE_P(REGNO) \ 974 aarch64_regno_ok_for_base_p (REGNO, true) 975 976 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 977 aarch64_regno_ok_for_index_p (REGNO, true) 978 979 #define LEGITIMATE_PIC_OPERAND_P(X) \ 980 aarch64_legitimate_pic_operand_p (X) 981 982 #define CASE_VECTOR_MODE Pmode 983 984 #define DEFAULT_SIGNED_CHAR 0 985 986 /* An integer expression for the size in bits of the largest integer machine 987 mode that should actually be used. We allow pairs of registers. */ 988 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 989 990 /* Maximum bytes moved by a single instruction (load/store pair). */ 991 #define MOVE_MAX (UNITS_PER_WORD * 2) 992 993 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 994 #define AARCH64_CALL_RATIO 8 995 996 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 997 move_by_pieces will continually copy the largest safe chunks. So a 998 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 999 for both size and speed of copy, so we will instead use the "cpymem" 1000 standard name to implement the copy. This logic does not apply when 1001 targeting -mstrict-align, so keep a sensible default in that case. */ 1002 #define MOVE_RATIO(speed) \ 1003 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 1004 1005 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 1006 of the length of a memset call, but use the default otherwise. */ 1007 #define CLEAR_RATIO(speed) \ 1008 ((speed) ? 15 : AARCH64_CALL_RATIO) 1009 1010 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 1011 optimizing for size adjust the ratio to account for the overhead of loading 1012 the constant. */ 1013 #define SET_RATIO(speed) \ 1014 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 1015 1016 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 1017 rarely a good idea in straight-line code since it adds an extra address 1018 dependency between each instruction. Better to use incrementing offsets. */ 1019 #define USE_LOAD_POST_INCREMENT(MODE) 0 1020 #define USE_LOAD_POST_DECREMENT(MODE) 0 1021 #define USE_LOAD_PRE_INCREMENT(MODE) 0 1022 #define USE_LOAD_PRE_DECREMENT(MODE) 0 1023 #define USE_STORE_POST_INCREMENT(MODE) 0 1024 #define USE_STORE_POST_DECREMENT(MODE) 0 1025 #define USE_STORE_PRE_INCREMENT(MODE) 0 1026 #define USE_STORE_PRE_DECREMENT(MODE) 0 1027 1028 /* WORD_REGISTER_OPERATIONS does not hold for AArch64. 1029 The assigned word_mode is DImode but operations narrower than SImode 1030 behave as 32-bit operations if using the W-form of the registers rather 1031 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 1032 expects. */ 1033 #define WORD_REGISTER_OPERATIONS 0 1034 1035 /* Define if loading from memory in MODE, an integral mode narrower than 1036 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 1037 macro should be the code that says which one of the two operations is 1038 implicitly done, or UNKNOWN if none. */ 1039 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1040 1041 /* Define this macro to be non-zero if instructions will fail to work 1042 if given data not on the nominal alignment. */ 1043 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 1044 1045 /* Enable wide bitfield accesses for more efficient bitfield code. */ 1046 #define SLOW_BYTE_ACCESS 1 1047 1048 #define NO_FUNCTION_CSE 1 1049 1050 /* Specify the machine mode that the hardware addresses have. 1051 After generation of rtl, the compiler makes no further distinction 1052 between pointers and any other objects of this machine mode. */ 1053 #define Pmode DImode 1054 1055 /* A C expression whose value is zero if pointers that need to be extended 1056 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1057 greater then zero if they are zero-extended and less then zero if the 1058 ptr_extend instruction should be used. */ 1059 #define POINTERS_EXTEND_UNSIGNED 1 1060 1061 /* Mode of a function address in a call instruction (for indexing purposes). */ 1062 #define FUNCTION_MODE Pmode 1063 1064 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 1065 1066 /* Having an integer comparison mode guarantees that we can use 1067 reverse_condition, but the usual restrictions apply to floating-point 1068 comparisons. */ 1069 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode) 1070 1071 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1072 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1073 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1074 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1075 1076 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 1077 1078 #define RETURN_ADDR_RTX aarch64_return_addr 1079 1080 /* BTI c + 3 insns 1081 + sls barrier of DSB + ISB. 1082 + 2 pointer-sized entries. */ 1083 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16)) 1084 1085 /* Trampolines contain dwords, so must be dword aligned. */ 1086 #define TRAMPOLINE_ALIGNMENT 64 1087 1088 /* Put trampolines in the text section so that mapping symbols work 1089 correctly. */ 1090 #define TRAMPOLINE_SECTION text_section 1091 1092 /* To start with. */ 1093 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1094 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 1095 1096 1097 /* Assembly output. */ 1098 1099 /* For now we'll make all jump tables pc-relative. */ 1100 #define CASE_VECTOR_PC_RELATIVE 1 1101 1102 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1103 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 1104 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 1105 : QImode) 1106 1107 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 1108 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 1109 1110 #define MCOUNT_NAME "_mcount" 1111 1112 #define NO_PROFILE_COUNTERS 1 1113 1114 /* Emit rtl for profiling. Output assembler code to FILE 1115 to call "_mcount" for profiling a function entry. */ 1116 #define PROFILE_HOOK(LABEL) \ 1117 { \ 1118 rtx fun, lr; \ 1119 lr = aarch64_return_addr_rtx (); \ 1120 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 1121 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ 1122 } 1123 1124 /* All the work done in PROFILE_HOOK, but still required. */ 1125 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 1126 1127 /* For some reason, the Linux headers think they know how to define 1128 these macros. They don't!!! */ 1129 #undef ASM_APP_ON 1130 #undef ASM_APP_OFF 1131 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 1132 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 1133 1134 #define CONSTANT_POOL_BEFORE_FUNCTION 0 1135 1136 /* This definition should be relocated to aarch64-elf-raw.h. This macro 1137 should be undefined in aarch64-linux.h and a clear_cache pattern 1138 implmented to emit either the call to __aarch64_sync_cache_range() 1139 directly or preferably the appropriate sycall or cache clear 1140 instructions inline. */ 1141 #define CLEAR_INSN_CACHE(beg, end) \ 1142 extern void __aarch64_sync_cache_range (void *, void *); \ 1143 __aarch64_sync_cache_range (beg, end) 1144 1145 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 1146 1147 /* Choose appropriate mode for caller saves, so we do the minimum 1148 required size of load/store. */ 1149 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1150 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 1151 1152 #undef SWITCHABLE_TARGET 1153 #define SWITCHABLE_TARGET 1 1154 1155 /* Check TLS Descriptors mechanism is selected. */ 1156 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 1157 1158 extern enum aarch64_code_model aarch64_cmodel; 1159 1160 /* When using the tiny addressing model conditional and unconditional branches 1161 can span the whole of the available address space (1MB). */ 1162 #define HAS_LONG_COND_BRANCH \ 1163 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1164 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1165 1166 #define HAS_LONG_UNCOND_BRANCH \ 1167 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1168 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1169 1170 #define TARGET_SUPPORTS_WIDE_INT 1 1171 1172 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 1173 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 1174 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1175 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 1176 || (MODE) == DFmode || (MODE) == V4BFmode) 1177 1178 /* Modes valid for AdvSIMD Q registers. */ 1179 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 1180 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1181 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 1182 || (MODE) == V2DFmode || (MODE) == V8BFmode) 1183 1184 #define ENDIAN_LANE_N(NUNITS, N) \ 1185 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) 1186 1187 /* Support for configure-time --with-arch, --with-cpu and --with-tune. 1188 --with-arch and --with-cpu are ignored if either -mcpu or -march is used. 1189 --with-tune is ignored if either -mtune or -mcpu is used (but is not 1190 affected by -march). */ 1191 #define OPTION_DEFAULT_SPECS \ 1192 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 1193 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 1194 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, 1195 1196 #define MCPU_TO_MARCH_SPEC \ 1197 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 1198 1199 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 1200 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 1201 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 1202 1203 #if defined(__aarch64__) 1204 extern const char *host_detect_local_cpu (int argc, const char **argv); 1205 #define HAVE_LOCAL_CPU_DETECT 1206 # define EXTRA_SPEC_FUNCTIONS \ 1207 { "local_cpu_detect", host_detect_local_cpu }, \ 1208 MCPU_TO_MARCH_SPEC_FUNCTIONS 1209 1210 # define MCPU_MTUNE_NATIVE_SPECS \ 1211 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 1212 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 1213 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 1214 #else 1215 # define MCPU_MTUNE_NATIVE_SPECS "" 1216 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 1217 #endif 1218 1219 #define ASM_CPU_SPEC \ 1220 MCPU_TO_MARCH_SPEC 1221 1222 #define EXTRA_SPECS \ 1223 { "asm_cpu_spec", ASM_CPU_SPEC } 1224 1225 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 1226 1227 /* This type is the user-visible __fp16, and a pointer to that type. We 1228 need it in many places in the backend. Defined in aarch64-builtins.c. */ 1229 extern tree aarch64_fp16_type_node; 1230 extern tree aarch64_fp16_ptr_type_node; 1231 1232 /* This type is the user-visible __bf16, and a pointer to that type. Defined 1233 in aarch64-builtins.c. */ 1234 extern tree aarch64_bf16_type_node; 1235 extern tree aarch64_bf16_ptr_type_node; 1236 1237 /* The generic unwind code in libgcc does not initialize the frame pointer. 1238 So in order to unwind a function using a frame pointer, the very first 1239 function that is unwound must save the frame pointer. That way the frame 1240 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 1241 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 1242 #define LIBGCC2_UNWIND_ATTRIBUTE \ 1243 __attribute__((optimize ("no-omit-frame-pointer"))) 1244 1245 #ifndef USED_FOR_TARGET 1246 extern poly_uint16 aarch64_sve_vg; 1247 1248 /* The number of bits and bytes in an SVE vector. */ 1249 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) 1250 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) 1251 1252 /* The number of bits and bytes in an SVE predicate. */ 1253 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR 1254 #define BYTES_PER_SVE_PRED aarch64_sve_vg 1255 1256 /* The SVE mode for a vector of bytes. */ 1257 #define SVE_BYTE_MODE VNx16QImode 1258 1259 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes 1260 (for -msve-vector-bits=2048) multiplied by the maximum number of 1261 vectors in a structure mode (4). 1262 1263 This limit must not be used for variable-size vectors, since 1264 VL-agnostic code must work with arbitary vector lengths. */ 1265 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) 1266 #endif 1267 1268 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) 1269 1270 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the 1271 outgoing arguments if stack clash protection is enabled. This is essential 1272 as the extra arg space allows us to skip a check in alloca. */ 1273 #undef STACK_DYNAMIC_OFFSET 1274 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1275 ((flag_stack_clash_protection \ 1276 && cfun->calls_alloca \ 1277 && known_lt (crtl->outgoing_args_size, \ 1278 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ 1279 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ 1280 STACK_BOUNDARY / BITS_PER_UNIT) \ 1281 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) 1282 1283 #endif /* GCC_AARCH64_H */ 1284