1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/rockchip/cpu.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
38
39 #include "core.h"
40 #include "pinconf.h"
41 #include "pinctrl-rockchip.h"
42
43 /*
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
45 * register 31:16 area.
46 */
47 #define WRITE_MASK_VAL(h, l, v) \
48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
49
50 /*
51 * Encode variants of iomux registers into a type variable
52 */
53 #define IOMUX_GPIO_ONLY BIT(0)
54 #define IOMUX_WIDTH_4BIT BIT(1)
55 #define IOMUX_SOURCE_PMU BIT(2)
56 #define IOMUX_UNROUTED BIT(3)
57 #define IOMUX_WIDTH_3BIT BIT(4)
58 #define IOMUX_WIDTH_2BIT BIT(5)
59 #define IOMUX_WRITABLE_32BIT BIT(6)
60 #define IOMUX_L_SOURCE_PMU BIT(7)
61
62 #define PIN_BANK(id, pins, label) \
63 { \
64 .bank_num = id, \
65 .nr_pins = pins, \
66 .name = label, \
67 .iomux = { \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
71 { .offset = -1 }, \
72 }, \
73 }
74
75 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
76 { \
77 .bank_num = id, \
78 .nr_pins = pins, \
79 .name = label, \
80 .iomux = { \
81 { .type = iom0, .offset = -1 }, \
82 { .type = iom1, .offset = -1 }, \
83 { .type = iom2, .offset = -1 }, \
84 { .type = iom3, .offset = -1 }, \
85 }, \
86 }
87
88 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
89 iom3, offset0, offset1, offset2, \
90 offset3) \
91 { \
92 .bank_num = id, \
93 .nr_pins = pins, \
94 .name = label, \
95 .iomux = { \
96 { .type = iom0, .offset = offset0 }, \
97 { .type = iom1, .offset = offset1 }, \
98 { .type = iom2, .offset = offset2 }, \
99 { .type = iom3, .offset = offset3 }, \
100 }, \
101 }
102
103 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
104 { \
105 .bank_num = id, \
106 .nr_pins = pins, \
107 .name = label, \
108 .iomux = { \
109 { .offset = -1 }, \
110 { .offset = -1 }, \
111 { .offset = -1 }, \
112 { .offset = -1 }, \
113 }, \
114 .drv = { \
115 { .drv_type = type0, .offset = -1 }, \
116 { .drv_type = type1, .offset = -1 }, \
117 { .drv_type = type2, .offset = -1 }, \
118 { .drv_type = type3, .offset = -1 }, \
119 }, \
120 }
121
122 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
123 iom2, iom3, pull0, pull1, \
124 pull2, pull3) \
125 { \
126 .bank_num = id, \
127 .nr_pins = pins, \
128 .name = label, \
129 .iomux = { \
130 { .type = iom0, .offset = -1 }, \
131 { .type = iom1, .offset = -1 }, \
132 { .type = iom2, .offset = -1 }, \
133 { .type = iom3, .offset = -1 }, \
134 }, \
135 .pull_type[0] = pull0, \
136 .pull_type[1] = pull1, \
137 .pull_type[2] = pull2, \
138 .pull_type[3] = pull3, \
139 }
140
141 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
142 drv2, drv3, pull0, pull1, \
143 pull2, pull3) \
144 { \
145 .bank_num = id, \
146 .nr_pins = pins, \
147 .name = label, \
148 .iomux = { \
149 { .offset = -1 }, \
150 { .offset = -1 }, \
151 { .offset = -1 }, \
152 { .offset = -1 }, \
153 }, \
154 .drv = { \
155 { .drv_type = drv0, .offset = -1 }, \
156 { .drv_type = drv1, .offset = -1 }, \
157 { .drv_type = drv2, .offset = -1 }, \
158 { .drv_type = drv3, .offset = -1 }, \
159 }, \
160 .pull_type[0] = pull0, \
161 .pull_type[1] = pull1, \
162 .pull_type[2] = pull2, \
163 .pull_type[3] = pull3, \
164 }
165
166 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
167 iom2, iom3, drv0, drv1, drv2, \
168 drv3, offset0, offset1, \
169 offset2, offset3) \
170 { \
171 .bank_num = id, \
172 .nr_pins = pins, \
173 .name = label, \
174 .iomux = { \
175 { .type = iom0, .offset = -1 }, \
176 { .type = iom1, .offset = -1 }, \
177 { .type = iom2, .offset = -1 }, \
178 { .type = iom3, .offset = -1 }, \
179 }, \
180 .drv = { \
181 { .drv_type = drv0, .offset = offset0 }, \
182 { .drv_type = drv1, .offset = offset1 }, \
183 { .drv_type = drv2, .offset = offset2 }, \
184 { .drv_type = drv3, .offset = offset3 }, \
185 }, \
186 }
187
188 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
189 label, iom0, iom1, iom2, \
190 iom3, drv0, drv1, drv2, \
191 drv3, offset0, offset1, \
192 offset2, offset3, pull0, \
193 pull1, pull2, pull3) \
194 { \
195 .bank_num = id, \
196 .nr_pins = pins, \
197 .name = label, \
198 .iomux = { \
199 { .type = iom0, .offset = -1 }, \
200 { .type = iom1, .offset = -1 }, \
201 { .type = iom2, .offset = -1 }, \
202 { .type = iom3, .offset = -1 }, \
203 }, \
204 .drv = { \
205 { .drv_type = drv0, .offset = offset0 }, \
206 { .drv_type = drv1, .offset = offset1 }, \
207 { .drv_type = drv2, .offset = offset2 }, \
208 { .drv_type = drv3, .offset = offset3 }, \
209 }, \
210 .pull_type[0] = pull0, \
211 .pull_type[1] = pull1, \
212 .pull_type[2] = pull2, \
213 .pull_type[3] = pull3, \
214 }
215
216 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
217 { \
218 .bank_num = ID, \
219 .pin = PIN, \
220 .func = FUNC, \
221 .route_offset = REG, \
222 .route_val = VAL, \
223 .route_location = FLAG, \
224 }
225
226 #define S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
227 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
228 MTYPE, MTYPE, MTYPE, MTYPE, \
229 DTYPE, DTYPE, DTYPE, DTYPE, \
230 -1, -1, -1, -1)
231
232 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
233 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
234
235 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
236 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
237
238 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
239 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
240
241 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
242 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
243
244 static struct pinctrl_dev *g_pctldev;
245 static DEFINE_MUTEX(iomux_lock);
246
247 static struct regmap_config rockchip_regmap_config = {
248 .reg_bits = 32,
249 .val_bits = 32,
250 .reg_stride = 4,
251 };
252
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)253 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
254 const struct rockchip_pinctrl *info,
255 const char *name)
256 {
257 int i;
258
259 for (i = 0; i < info->ngroups; i++) {
260 if (!strcmp(info->groups[i].name, name))
261 return &info->groups[i];
262 }
263
264 return NULL;
265 }
266
267 /*
268 * given a pin number that is local to a pin controller, find out the pin bank
269 * and the register base of the pin bank.
270 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)271 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
272 unsigned pin)
273 {
274 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
275
276 while (pin >= (b->pin_base + b->nr_pins))
277 b++;
278
279 return b;
280 }
281
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)282 static struct rockchip_pin_bank *bank_num_to_bank(
283 struct rockchip_pinctrl *info,
284 unsigned num)
285 {
286 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
287 int i;
288
289 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
290 if (b->bank_num == num)
291 return b;
292 }
293
294 return ERR_PTR(-EINVAL);
295 }
296
297 /*
298 * Pinctrl_ops handling
299 */
300
rockchip_get_groups_count(struct pinctrl_dev * pctldev)301 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
302 {
303 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
304
305 return info->ngroups;
306 }
307
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)308 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
309 unsigned selector)
310 {
311 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
312
313 return info->groups[selector].name;
314 }
315
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)316 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
317 unsigned selector, const unsigned **pins,
318 unsigned *npins)
319 {
320 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
321
322 if (selector >= info->ngroups)
323 return -EINVAL;
324
325 *pins = info->groups[selector].pins;
326 *npins = info->groups[selector].npins;
327
328 return 0;
329 }
330
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)331 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
332 struct device_node *np,
333 struct pinctrl_map **map, unsigned *num_maps)
334 {
335 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
336 const struct rockchip_pin_group *grp;
337 struct device *dev = info->dev;
338 struct pinctrl_map *new_map;
339 struct device_node *parent;
340 int map_num = 1;
341 int i;
342
343 /*
344 * first find the group of this node and check if we need to create
345 * config maps for pins
346 */
347 grp = pinctrl_name_to_group(info, np->name);
348 if (!grp) {
349 dev_err(dev, "unable to find group for node %pOFn\n", np);
350 return -EINVAL;
351 }
352
353 map_num += grp->npins;
354
355 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
356 if (!new_map)
357 return -ENOMEM;
358
359 *map = new_map;
360 *num_maps = map_num;
361
362 /* create mux map */
363 parent = of_get_parent(np);
364 if (!parent) {
365 kfree(new_map);
366 return -EINVAL;
367 }
368 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
369 new_map[0].data.mux.function = parent->name;
370 new_map[0].data.mux.group = np->name;
371 of_node_put(parent);
372
373 /* create config map */
374 new_map++;
375 for (i = 0; i < grp->npins; i++) {
376 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
377 new_map[i].data.configs.group_or_pin =
378 pin_get_name(pctldev, grp->pins[i]);
379 new_map[i].data.configs.configs = grp->data[i].configs;
380 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
381 }
382
383 dev_dbg(dev, "maps: function %s group %s num %d\n",
384 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
385
386 return 0;
387 }
388
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)389 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
390 struct pinctrl_map *map, unsigned num_maps)
391 {
392 kfree(map);
393 }
394
395 static const struct pinctrl_ops rockchip_pctrl_ops = {
396 .get_groups_count = rockchip_get_groups_count,
397 .get_group_name = rockchip_get_group_name,
398 .get_group_pins = rockchip_get_group_pins,
399 .dt_node_to_map = rockchip_dt_node_to_map,
400 .dt_free_map = rockchip_dt_free_map,
401 };
402
403 /*
404 * Hardware access
405 */
406
407 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
408 {
409 .num = 1,
410 .pin = 0,
411 .reg = 0x418,
412 .bit = 0,
413 .mask = 0x3
414 }, {
415 .num = 1,
416 .pin = 1,
417 .reg = 0x418,
418 .bit = 2,
419 .mask = 0x3
420 }, {
421 .num = 1,
422 .pin = 2,
423 .reg = 0x418,
424 .bit = 4,
425 .mask = 0x3
426 }, {
427 .num = 1,
428 .pin = 3,
429 .reg = 0x418,
430 .bit = 6,
431 .mask = 0x3
432 }, {
433 .num = 1,
434 .pin = 4,
435 .reg = 0x418,
436 .bit = 8,
437 .mask = 0x3
438 }, {
439 .num = 1,
440 .pin = 5,
441 .reg = 0x418,
442 .bit = 10,
443 .mask = 0x3
444 }, {
445 .num = 1,
446 .pin = 6,
447 .reg = 0x418,
448 .bit = 12,
449 .mask = 0x3
450 }, {
451 .num = 1,
452 .pin = 7,
453 .reg = 0x418,
454 .bit = 14,
455 .mask = 0x3
456 }, {
457 .num = 1,
458 .pin = 8,
459 .reg = 0x41c,
460 .bit = 0,
461 .mask = 0x3
462 }, {
463 .num = 1,
464 .pin = 9,
465 .reg = 0x41c,
466 .bit = 2,
467 .mask = 0x3
468 },
469 };
470
471 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
472 {
473 .num = 0,
474 .pin = 20,
475 .reg = 0x10000,
476 .bit = 0,
477 .mask = 0xf
478 },
479 {
480 .num = 0,
481 .pin = 21,
482 .reg = 0x10000,
483 .bit = 4,
484 .mask = 0xf
485 },
486 {
487 .num = 0,
488 .pin = 22,
489 .reg = 0x10000,
490 .bit = 8,
491 .mask = 0xf
492 },
493 {
494 .num = 0,
495 .pin = 23,
496 .reg = 0x10000,
497 .bit = 12,
498 .mask = 0xf
499 },
500 };
501
502 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
503 {
504 .num = 2,
505 .pin = 20,
506 .reg = 0xe8,
507 .bit = 0,
508 .mask = 0x7
509 }, {
510 .num = 2,
511 .pin = 21,
512 .reg = 0xe8,
513 .bit = 4,
514 .mask = 0x7
515 }, {
516 .num = 2,
517 .pin = 22,
518 .reg = 0xe8,
519 .bit = 8,
520 .mask = 0x7
521 }, {
522 .num = 2,
523 .pin = 23,
524 .reg = 0xe8,
525 .bit = 12,
526 .mask = 0x7
527 }, {
528 .num = 2,
529 .pin = 24,
530 .reg = 0xd4,
531 .bit = 12,
532 .mask = 0x7
533 },
534 };
535
536 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
537 {
538 /* gpio1b6_sel */
539 .num = 1,
540 .pin = 14,
541 .reg = 0x28,
542 .bit = 12,
543 .mask = 0xf
544 }, {
545 /* gpio1b7_sel */
546 .num = 1,
547 .pin = 15,
548 .reg = 0x2c,
549 .bit = 0,
550 .mask = 0x3
551 }, {
552 /* gpio1c2_sel */
553 .num = 1,
554 .pin = 18,
555 .reg = 0x30,
556 .bit = 4,
557 .mask = 0xf
558 }, {
559 /* gpio1c3_sel */
560 .num = 1,
561 .pin = 19,
562 .reg = 0x30,
563 .bit = 8,
564 .mask = 0xf
565 }, {
566 /* gpio1c4_sel */
567 .num = 1,
568 .pin = 20,
569 .reg = 0x30,
570 .bit = 12,
571 .mask = 0xf
572 }, {
573 /* gpio1c5_sel */
574 .num = 1,
575 .pin = 21,
576 .reg = 0x34,
577 .bit = 0,
578 .mask = 0xf
579 }, {
580 /* gpio1c6_sel */
581 .num = 1,
582 .pin = 22,
583 .reg = 0x34,
584 .bit = 4,
585 .mask = 0xf
586 }, {
587 /* gpio1c7_sel */
588 .num = 1,
589 .pin = 23,
590 .reg = 0x34,
591 .bit = 8,
592 .mask = 0xf
593 }, {
594 /* gpio2a2_sel_plus */
595 .num = 2,
596 .pin = 2,
597 .reg = 0x608,
598 .bit = 0,
599 .mask = 0x7
600 }, {
601 /* gpio2a3_sel_plus */
602 .num = 2,
603 .pin = 3,
604 .reg = 0x608,
605 .bit = 4,
606 .mask = 0x7
607 }, {
608 /* gpio2c0_sel_plus */
609 .num = 2,
610 .pin = 16,
611 .reg = 0x610,
612 .bit = 8,
613 .mask = 0x7
614 }, {
615 /* gpio3b2_sel_plus */
616 .num = 3,
617 .pin = 10,
618 .reg = 0x610,
619 .bit = 0,
620 .mask = 0x7
621 }, {
622 /* gpio3b3_sel_plus */
623 .num = 3,
624 .pin = 11,
625 .reg = 0x610,
626 .bit = 4,
627 .mask = 0x7
628 }, {
629 /* gpio3b4_sel */
630 .num = 3,
631 .pin = 12,
632 .reg = 0x68,
633 .bit = 8,
634 .mask = 0xf
635 }, {
636 /* gpio3b5_sel */
637 .num = 3,
638 .pin = 13,
639 .reg = 0x68,
640 .bit = 12,
641 .mask = 0xf
642 },
643 };
644
645 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
646 {
647 .num = 2,
648 .pin = 8,
649 .reg = 0x24,
650 .bit = 0,
651 .mask = 0x3
652 }, {
653 .num = 2,
654 .pin = 9,
655 .reg = 0x24,
656 .bit = 2,
657 .mask = 0x3
658 }, {
659 .num = 2,
660 .pin = 10,
661 .reg = 0x24,
662 .bit = 4,
663 .mask = 0x3
664 }, {
665 .num = 2,
666 .pin = 11,
667 .reg = 0x24,
668 .bit = 6,
669 .mask = 0x3
670 }, {
671 .num = 2,
672 .pin = 12,
673 .reg = 0x24,
674 .bit = 8,
675 .mask = 0x3
676 }, {
677 .num = 2,
678 .pin = 13,
679 .reg = 0x24,
680 .bit = 10,
681 .mask = 0x3
682 }, {
683 .num = 2,
684 .pin = 14,
685 .reg = 0x24,
686 .bit = 12,
687 .mask = 0x3
688 }, {
689 .num = 2,
690 .pin = 15,
691 .reg = 0x28,
692 .bit = 0,
693 .mask = 0x7
694 }, {
695 .num = 2,
696 .pin = 23,
697 .reg = 0x30,
698 .bit = 14,
699 .mask = 0x3
700 },
701 };
702
703 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
704 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
705 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
706
707 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
708 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
709 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
710
711 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
712 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
713
714 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
715 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
716
717 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
718 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
719
720 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
721 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
722 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
723
724 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
725 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
726
727 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
728 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
729 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
730
731 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
732 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
733 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
734
735 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
736 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
737
738 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
739 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
740
741 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
742 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
743
744 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
745 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
746
747 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
748 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
749
750 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
751 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
752
753 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
754 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
755
756 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
757 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
758 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
759
760 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
761 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
762 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
763
764 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
765 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
766 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
767
768 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
769 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
770
771 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
772 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
773
774 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
775 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
776
777 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
778 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
779
780 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
781 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
782
783 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
784 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
785
786 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
787 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
788
789 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
790 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
791
792 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
793 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
794 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
795
796 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
797 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
798 };
799
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)800 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
801 int *reg, u8 *bit, int *mask)
802 {
803 struct rockchip_pinctrl *info = bank->drvdata;
804 struct rockchip_pin_ctrl *ctrl = info->ctrl;
805 struct rockchip_mux_recalced_data *data;
806 int i;
807
808 for (i = 0; i < ctrl->niomux_recalced; i++) {
809 data = &ctrl->iomux_recalced[i];
810 if (data->num == bank->bank_num &&
811 data->pin == pin)
812 break;
813 }
814
815 if (i >= ctrl->niomux_recalced)
816 return;
817
818 *reg = data->reg;
819 *mask = data->mask;
820 *bit = data->bit;
821 }
822
823 static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
824 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x190, BIT(16 + 3)), /* i2c2m0_sda */
825 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x190, BIT(16 + 3) | BIT(3)), /* i2c2m1_sda */
826 RK_MUXROUTE_SAME(1, RK_PA6, 2, 0x190, BIT(16 + 4)), /* spi2m0_miso */
827 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x190, BIT(16 + 4) | BIT(4)), /* spi2m1_miso */
828 RK_MUXROUTE_SAME(4, RK_PB7, 2, 0x190, BIT(16 + 5)), /* spi1m0_miso */
829 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x190, BIT(16 + 5) | BIT(5)), /* spi1m1_miso */
830 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0x190, BIT(16 + 13)), /* uart1_rxm0 */
831 RK_MUXROUTE_SAME(1, RK_PB4, 3, 0x190, BIT(16 + 13) | BIT(13)), /* uart1_rxm1 */
832 RK_MUXROUTE_SAME(4, RK_PA3, 2, 0x190, BIT(16 + 14) | BIT(16 + 15)), /* uart2_rxm0 */
833 RK_MUXROUTE_SAME(2, RK_PD1, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(14)), /* uart2_rxm1 */
834 RK_MUXROUTE_SAME(3, RK_PA4, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(15)), /* uart2_rxm2 */
835 };
836
837 static struct rockchip_mux_route_data px30_mux_route_data[] = {
838 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
839 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
840 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
841 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
842 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
843 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
844 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
845 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
846 };
847
848 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
849 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
850 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
851 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
852 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
853 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
854 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
855 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
856 };
857
858 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
859 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
860 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
861 };
862
863 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
864 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
865 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
866 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
867 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
868 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
869 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
870 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
871 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
872 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
873 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
874 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
875 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
876 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
877 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
878 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
879 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
880 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
881 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
882 };
883
884 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
885 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
886 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
887 };
888
889 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
890 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
891 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
892 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
893 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
894 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
895 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
896 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
897 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
898 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
899 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
900 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
901 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
902 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
903 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
904 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
905 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
906 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
907 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
908 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
909 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
910 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
911 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
912 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
913 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
914 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
915 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
916 };
917
918 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
919 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
920 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
921 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
922 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
923 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
924 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
925 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
926 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
927 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
928 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
929 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
930 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
931 };
932
933 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
934 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
935 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
936 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
937 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
938 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
939 };
940
941 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
942 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
943 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
944 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
945 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
946 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
947 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
948 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
949 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
950 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
951 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
952 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
953 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
954 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
955 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
956 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
957 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
958 RK_MUXROUTE_GRF(4, RK_PB7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
959 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
960 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
961 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
962 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
963 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
964 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
965 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
966 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
967 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
968 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
969 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
970 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
971 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
972 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
973 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
974 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
975 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
976 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
977 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
978 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
979 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
980 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
981 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
982 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
983 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
984 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
985 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
986 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
987 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
988 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
989 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
990 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
991 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
992 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
993 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
994 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
995 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
996 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
997 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
998 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
999 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1000 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1001 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1002 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1003 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1004 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1005 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1006 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1007 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1008 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1009 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1010 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1011 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1012 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1013 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1014 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1015 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1016 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1017 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1018 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1019 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1020 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1021 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1022 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1023 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1024 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1025 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1026 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1027 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1028 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1029 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1030 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1031 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1032 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1033 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1034 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1035 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1036 };
1037
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)1038 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1039 int mux, u32 *loc, u32 *reg, u32 *value)
1040 {
1041 struct rockchip_pinctrl *info = bank->drvdata;
1042 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1043 struct rockchip_mux_route_data *data;
1044 int i;
1045
1046 for (i = 0; i < ctrl->niomux_routes; i++) {
1047 data = &ctrl->iomux_routes[i];
1048 if ((data->bank_num == bank->bank_num) &&
1049 (data->pin == pin) && (data->func == mux))
1050 break;
1051 }
1052
1053 if (i >= ctrl->niomux_routes)
1054 return false;
1055
1056 *loc = data->route_location;
1057 *reg = data->route_offset;
1058 *value = data->route_val;
1059
1060 return true;
1061 }
1062
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1063 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1064 {
1065 struct rockchip_pinctrl *info = bank->drvdata;
1066 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1067 int iomux_num = (pin / 8);
1068 struct regmap *regmap;
1069 unsigned int val;
1070 int reg, ret, mask, mux_type;
1071 u8 bit;
1072
1073 if (iomux_num > 3)
1074 return -EINVAL;
1075
1076 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1077 dev_err(info->dev, "pin %d is unrouted\n", pin);
1078 return -EINVAL;
1079 }
1080
1081 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1082 return RK_FUNC_GPIO;
1083
1084 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1085 regmap = info->regmap_pmu;
1086 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1087 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1088 else
1089 regmap = info->regmap_base;
1090
1091 /* get basic quadrupel of mux registers and the correct reg inside */
1092 mux_type = bank->iomux[iomux_num].type;
1093 reg = bank->iomux[iomux_num].offset;
1094 if (mux_type & IOMUX_WIDTH_4BIT) {
1095 if ((pin % 8) >= 4)
1096 reg += 0x4;
1097 bit = (pin % 4) * 4;
1098 mask = 0xf;
1099 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1100 if ((pin % 8) >= 5)
1101 reg += 0x4;
1102 bit = (pin % 8 % 5) * 3;
1103 mask = 0x7;
1104 } else {
1105 bit = (pin % 8) * 2;
1106 mask = 0x3;
1107 }
1108
1109 if (bank->recalced_mask & BIT(pin))
1110 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1111
1112 if (ctrl->type == RK3588) {
1113 if (bank->bank_num == 0) {
1114 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1115 u32 reg0 = 0;
1116
1117 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1118 ret = regmap_read(regmap, reg0, &val);
1119 if (ret)
1120 return ret;
1121
1122 if (((val >> bit) & mask) != 8)
1123 return ((val >> bit) & mask);
1124
1125 reg = reg + 0x8000; /* BUS_IOC_BASE */
1126 regmap = info->regmap_base;
1127 }
1128 } else if (bank->bank_num > 0) {
1129 reg += 0x8000; /* BUS_IOC_BASE */
1130 }
1131 }
1132
1133 ret = regmap_read(regmap, reg, &val);
1134 if (ret)
1135 return ret;
1136
1137 return ((val >> bit) & mask);
1138 }
1139
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1140 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1141 int pin, int mux)
1142 {
1143 struct rockchip_pinctrl *info = bank->drvdata;
1144 struct device *dev = info->dev;
1145 int iomux_num = (pin / 8);
1146
1147 if (iomux_num > 3)
1148 return -EINVAL;
1149
1150 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1151 dev_err(dev, "pin %d is unrouted\n", pin);
1152 return -EINVAL;
1153 }
1154
1155 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1156 if (mux != RK_FUNC_GPIO) {
1157 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1158 return -ENOTSUPP;
1159 }
1160 }
1161
1162 return 0;
1163 }
1164
1165 /*
1166 * Set a new mux function for a pin.
1167 *
1168 * The register is divided into the upper and lower 16 bit. When changing
1169 * a value, the previous register value is not read and changed. Instead
1170 * it seems the changed bits are marked in the upper 16 bit, while the
1171 * changed value gets set in the same offset in the lower 16 bit.
1172 * All pin settings seem to be 2 bit wide in both the upper and lower
1173 * parts.
1174 * @bank: pin bank to change
1175 * @pin: pin to change
1176 * @mux: new mux function to set
1177 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1178 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1179 {
1180 struct rockchip_pinctrl *info = bank->drvdata;
1181 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1182 struct device *dev = info->dev;
1183 int iomux_num = (pin / 8);
1184 struct regmap *regmap;
1185 int reg, ret, mask, mux_type;
1186 u8 bit;
1187 u32 data, rmask, route_location, route_reg, route_val;
1188
1189 ret = rockchip_verify_mux(bank, pin, mux);
1190 if (ret < 0)
1191 return ret;
1192
1193 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1194 return 0;
1195
1196 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1197
1198 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1199 regmap = info->regmap_pmu;
1200 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1201 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1202 else
1203 regmap = info->regmap_base;
1204
1205 /* get basic quadrupel of mux registers and the correct reg inside */
1206 mux_type = bank->iomux[iomux_num].type;
1207 reg = bank->iomux[iomux_num].offset;
1208 if (mux_type & IOMUX_WIDTH_4BIT) {
1209 if ((pin % 8) >= 4)
1210 reg += 0x4;
1211 bit = (pin % 4) * 4;
1212 mask = 0xf;
1213 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1214 if ((pin % 8) >= 5)
1215 reg += 0x4;
1216 bit = (pin % 8 % 5) * 3;
1217 mask = 0x7;
1218 } else {
1219 bit = (pin % 8) * 2;
1220 mask = 0x3;
1221 }
1222
1223 if (bank->recalced_mask & BIT(pin))
1224 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1225
1226 /* rk3562 force jtag m1 */
1227 if (ctrl->type == RK3562) {
1228 if (bank->bank_num == 1) {
1229 if ((pin == RK_PB5) || (pin == RK_PB6)) {
1230 if (mux == 1) {
1231 regmap_update_bits(regmap, 0x504, 0x10001, 0x10001);
1232 } else {
1233 regmap_update_bits(regmap, 0x504, 0x10001, 0x10000);
1234 }
1235 }
1236 }
1237 }
1238
1239 if (ctrl->type == RK3588) {
1240 if (bank->bank_num == 0) {
1241 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1242 if (mux < 8) {
1243 u32 reg0 = 0;
1244
1245 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1246 data = (mask << (bit + 16));
1247 rmask = data | (data >> 16);
1248 data |= (mux & mask) << bit;
1249 ret = regmap_update_bits(regmap, reg0, rmask, data);
1250
1251 reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1252 data = (mask << (bit + 16));
1253 rmask = data | (data >> 16);
1254 regmap = info->regmap_base;
1255 ret |= regmap_update_bits(regmap, reg0, rmask, data);
1256 } else {
1257 u32 reg0 = 0;
1258
1259 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1260 data = (mask << (bit + 16));
1261 rmask = data | (data >> 16);
1262 data |= 8 << bit;
1263 ret = regmap_update_bits(regmap, reg0, rmask, data);
1264
1265 reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1266 data = (mask << (bit + 16));
1267 rmask = data | (data >> 16);
1268 data |= (mux & mask) << bit;
1269 regmap = info->regmap_base;
1270 ret |= regmap_update_bits(regmap, reg0, rmask, data);
1271 }
1272 } else {
1273 data = (mask << (bit + 16));
1274 rmask = data | (data >> 16);
1275 data |= (mux & mask) << bit;
1276 ret = regmap_update_bits(regmap, reg, rmask, data);
1277 }
1278 return ret;
1279 } else if (bank->bank_num > 0) {
1280 reg += 0x8000; /* BUS_IOC_BASE */
1281 }
1282 }
1283
1284 if (mux > mask)
1285 return -EINVAL;
1286
1287 if (bank->route_mask & BIT(pin)) {
1288 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1289 &route_reg, &route_val)) {
1290 struct regmap *route_regmap = regmap;
1291
1292 /* handle special locations */
1293 switch (route_location) {
1294 case ROCKCHIP_ROUTE_PMU:
1295 route_regmap = info->regmap_pmu;
1296 break;
1297 case ROCKCHIP_ROUTE_GRF:
1298 route_regmap = info->regmap_base;
1299 break;
1300 }
1301
1302 ret = regmap_write(route_regmap, route_reg, route_val);
1303 if (ret)
1304 return ret;
1305 }
1306 }
1307
1308 if (mux_type & IOMUX_WRITABLE_32BIT) {
1309 ret = regmap_read(regmap, reg, &data);
1310 if (ret)
1311 return ret;
1312
1313 data &= ~(mask << bit);
1314 data |= (mux & mask) << bit;
1315 ret = regmap_write(regmap, reg, data);
1316 } else {
1317 data = (mask << (bit + 16));
1318 rmask = data | (data >> 16);
1319 data |= (mux & mask) << bit;
1320 ret = regmap_update_bits(regmap, reg, rmask, data);
1321 }
1322
1323 return ret;
1324 }
1325
1326 #define PX30_PULL_PMU_OFFSET 0x10
1327 #define PX30_PULL_GRF_OFFSET 0x60
1328 #define PX30_PULL_BITS_PER_PIN 2
1329 #define PX30_PULL_PINS_PER_REG 8
1330 #define PX30_PULL_BANK_STRIDE 16
1331
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1332 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1333 int pin_num, struct regmap **regmap,
1334 int *reg, u8 *bit)
1335 {
1336 struct rockchip_pinctrl *info = bank->drvdata;
1337
1338 /* The first 32 pins of the first bank are located in PMU */
1339 if (bank->bank_num == 0) {
1340 *regmap = info->regmap_pmu;
1341 *reg = PX30_PULL_PMU_OFFSET;
1342 } else {
1343 *regmap = info->regmap_base;
1344 *reg = PX30_PULL_GRF_OFFSET;
1345
1346 /* correct the offset, as we're starting with the 2nd bank */
1347 *reg -= 0x10;
1348 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1349 }
1350
1351 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1352 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1353 *bit *= PX30_PULL_BITS_PER_PIN;
1354
1355 return 0;
1356 }
1357
1358 #define PX30_DRV_PMU_OFFSET 0x20
1359 #define PX30_DRV_GRF_OFFSET 0xf0
1360 #define PX30_DRV_BITS_PER_PIN 2
1361 #define PX30_DRV_PINS_PER_REG 8
1362 #define PX30_DRV_BANK_STRIDE 16
1363
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1364 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1365 int pin_num, struct regmap **regmap,
1366 int *reg, u8 *bit)
1367 {
1368 struct rockchip_pinctrl *info = bank->drvdata;
1369
1370 /* The first 32 pins of the first bank are located in PMU */
1371 if (bank->bank_num == 0) {
1372 *regmap = info->regmap_pmu;
1373 *reg = PX30_DRV_PMU_OFFSET;
1374 } else {
1375 *regmap = info->regmap_base;
1376 *reg = PX30_DRV_GRF_OFFSET;
1377
1378 /* correct the offset, as we're starting with the 2nd bank */
1379 *reg -= 0x10;
1380 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1381 }
1382
1383 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1384 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1385 *bit *= PX30_DRV_BITS_PER_PIN;
1386
1387 return 0;
1388 }
1389
1390 #define PX30_SCHMITT_PMU_OFFSET 0x38
1391 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1392 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1393 #define PX30_SCHMITT_BANK_STRIDE 16
1394 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1395
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1396 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1397 int pin_num,
1398 struct regmap **regmap,
1399 int *reg, u8 *bit)
1400 {
1401 struct rockchip_pinctrl *info = bank->drvdata;
1402 int pins_per_reg;
1403
1404 if (bank->bank_num == 0) {
1405 *regmap = info->regmap_pmu;
1406 *reg = PX30_SCHMITT_PMU_OFFSET;
1407 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1408 } else {
1409 *regmap = info->regmap_base;
1410 *reg = PX30_SCHMITT_GRF_OFFSET;
1411 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1412 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1413 }
1414
1415 *reg += ((pin_num / pins_per_reg) * 4);
1416 *bit = pin_num % pins_per_reg;
1417
1418 return 0;
1419 }
1420
1421 #define RV1106_DRV_BITS_PER_PIN 8
1422 #define RV1106_DRV_PINS_PER_REG 2
1423 #define RV1106_DRV_GPIO0_OFFSET 0x10
1424 #define RV1106_DRV_GPIO1_OFFSET 0x80
1425 #define RV1106_DRV_GPIO2_OFFSET 0x100C0
1426 #define RV1106_DRV_GPIO3_OFFSET 0x20100
1427 #define RV1106_DRV_GPIO4_OFFSET 0x30020
1428
rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1429 static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1430 int pin_num, struct regmap **regmap,
1431 int *reg, u8 *bit)
1432 {
1433 struct rockchip_pinctrl *info = bank->drvdata;
1434
1435 /* GPIO0_IOC is located in PMU */
1436 switch (bank->bank_num) {
1437 case 0:
1438 *regmap = info->regmap_pmu;
1439 *reg = RV1106_DRV_GPIO0_OFFSET;
1440 break;
1441
1442 case 1:
1443 *regmap = info->regmap_base;
1444 *reg = RV1106_DRV_GPIO1_OFFSET;
1445 break;
1446
1447 case 2:
1448 *regmap = info->regmap_base;
1449 *reg = RV1106_DRV_GPIO2_OFFSET;
1450 break;
1451
1452 case 3:
1453 *regmap = info->regmap_base;
1454 *reg = RV1106_DRV_GPIO3_OFFSET;
1455 break;
1456
1457 case 4:
1458 *regmap = info->regmap_base;
1459 *reg = RV1106_DRV_GPIO4_OFFSET;
1460 break;
1461
1462 default:
1463 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
1464 break;
1465 }
1466
1467 *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4);
1468 *bit = pin_num % RV1106_DRV_PINS_PER_REG;
1469 *bit *= RV1106_DRV_BITS_PER_PIN;
1470
1471 return 0;
1472 }
1473
1474 #define RV1106_PULL_BITS_PER_PIN 2
1475 #define RV1106_PULL_PINS_PER_REG 8
1476 #define RV1106_PULL_GPIO0_OFFSET 0x38
1477 #define RV1106_PULL_GPIO1_OFFSET 0x1C0
1478 #define RV1106_PULL_GPIO2_OFFSET 0x101D0
1479 #define RV1106_PULL_GPIO3_OFFSET 0x201E0
1480 #define RV1106_PULL_GPIO4_OFFSET 0x30070
1481
rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1482 static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1483 int pin_num, struct regmap **regmap,
1484 int *reg, u8 *bit)
1485 {
1486 struct rockchip_pinctrl *info = bank->drvdata;
1487
1488 /* GPIO0_IOC is located in PMU */
1489 switch (bank->bank_num) {
1490 case 0:
1491 *regmap = info->regmap_pmu;
1492 *reg = RV1106_PULL_GPIO0_OFFSET;
1493 break;
1494
1495 case 1:
1496 *regmap = info->regmap_base;
1497 *reg = RV1106_PULL_GPIO1_OFFSET;
1498 break;
1499
1500 case 2:
1501 *regmap = info->regmap_base;
1502 *reg = RV1106_PULL_GPIO2_OFFSET;
1503 break;
1504
1505 case 3:
1506 *regmap = info->regmap_base;
1507 *reg = RV1106_PULL_GPIO3_OFFSET;
1508 break;
1509
1510 case 4:
1511 *regmap = info->regmap_base;
1512 *reg = RV1106_PULL_GPIO4_OFFSET;
1513 break;
1514
1515 default:
1516 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
1517 break;
1518 }
1519
1520 *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4);
1521 *bit = pin_num % RV1106_PULL_PINS_PER_REG;
1522 *bit *= RV1106_PULL_BITS_PER_PIN;
1523
1524 return 0;
1525 }
1526
1527 #define RV1106_SMT_BITS_PER_PIN 1
1528 #define RV1106_SMT_PINS_PER_REG 8
1529 #define RV1106_SMT_GPIO0_OFFSET 0x40
1530 #define RV1106_SMT_GPIO1_OFFSET 0x280
1531 #define RV1106_SMT_GPIO2_OFFSET 0x10290
1532 #define RV1106_SMT_GPIO3_OFFSET 0x202A0
1533 #define RV1106_SMT_GPIO4_OFFSET 0x300A0
1534
rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1535 static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1536 int pin_num,
1537 struct regmap **regmap,
1538 int *reg, u8 *bit)
1539 {
1540 struct rockchip_pinctrl *info = bank->drvdata;
1541
1542 /* GPIO0_IOC is located in PMU */
1543 switch (bank->bank_num) {
1544 case 0:
1545 *regmap = info->regmap_pmu;
1546 *reg = RV1106_SMT_GPIO0_OFFSET;
1547 break;
1548
1549 case 1:
1550 *regmap = info->regmap_base;
1551 *reg = RV1106_SMT_GPIO1_OFFSET;
1552 break;
1553
1554 case 2:
1555 *regmap = info->regmap_base;
1556 *reg = RV1106_SMT_GPIO2_OFFSET;
1557 break;
1558
1559 case 3:
1560 *regmap = info->regmap_base;
1561 *reg = RV1106_SMT_GPIO3_OFFSET;
1562 break;
1563
1564 case 4:
1565 *regmap = info->regmap_base;
1566 *reg = RV1106_SMT_GPIO4_OFFSET;
1567 break;
1568
1569 default:
1570 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
1571 break;
1572 }
1573
1574 *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4);
1575 *bit = pin_num % RV1106_SMT_PINS_PER_REG;
1576 *bit *= RV1106_SMT_BITS_PER_PIN;
1577
1578 return 0;
1579 }
1580
1581 #define RV1108_PULL_PMU_OFFSET 0x10
1582 #define RV1108_PULL_OFFSET 0x110
1583 #define RV1108_PULL_PINS_PER_REG 8
1584 #define RV1108_PULL_BITS_PER_PIN 2
1585 #define RV1108_PULL_BANK_STRIDE 16
1586
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1587 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1588 int pin_num, struct regmap **regmap,
1589 int *reg, u8 *bit)
1590 {
1591 struct rockchip_pinctrl *info = bank->drvdata;
1592
1593 /* The first 24 pins of the first bank are located in PMU */
1594 if (bank->bank_num == 0) {
1595 *regmap = info->regmap_pmu;
1596 *reg = RV1108_PULL_PMU_OFFSET;
1597 } else {
1598 *reg = RV1108_PULL_OFFSET;
1599 *regmap = info->regmap_base;
1600 /* correct the offset, as we're starting with the 2nd bank */
1601 *reg -= 0x10;
1602 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1603 }
1604
1605 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1606 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1607 *bit *= RV1108_PULL_BITS_PER_PIN;
1608
1609 return 0;
1610 }
1611
1612 #define RV1108_DRV_PMU_OFFSET 0x20
1613 #define RV1108_DRV_GRF_OFFSET 0x210
1614 #define RV1108_DRV_BITS_PER_PIN 2
1615 #define RV1108_DRV_PINS_PER_REG 8
1616 #define RV1108_DRV_BANK_STRIDE 16
1617
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1618 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1619 int pin_num, struct regmap **regmap,
1620 int *reg, u8 *bit)
1621 {
1622 struct rockchip_pinctrl *info = bank->drvdata;
1623
1624 /* The first 24 pins of the first bank are located in PMU */
1625 if (bank->bank_num == 0) {
1626 *regmap = info->regmap_pmu;
1627 *reg = RV1108_DRV_PMU_OFFSET;
1628 } else {
1629 *regmap = info->regmap_base;
1630 *reg = RV1108_DRV_GRF_OFFSET;
1631
1632 /* correct the offset, as we're starting with the 2nd bank */
1633 *reg -= 0x10;
1634 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1635 }
1636
1637 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1638 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1639 *bit *= RV1108_DRV_BITS_PER_PIN;
1640
1641 return 0;
1642 }
1643
1644 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1645 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1646 #define RV1108_SCHMITT_BANK_STRIDE 8
1647 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1648 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1649
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1650 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1651 int pin_num,
1652 struct regmap **regmap,
1653 int *reg, u8 *bit)
1654 {
1655 struct rockchip_pinctrl *info = bank->drvdata;
1656 int pins_per_reg;
1657
1658 if (bank->bank_num == 0) {
1659 *regmap = info->regmap_pmu;
1660 *reg = RV1108_SCHMITT_PMU_OFFSET;
1661 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1662 } else {
1663 *regmap = info->regmap_base;
1664 *reg = RV1108_SCHMITT_GRF_OFFSET;
1665 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1666 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1667 }
1668 *reg += ((pin_num / pins_per_reg) * 4);
1669 *bit = pin_num % pins_per_reg;
1670
1671 return 0;
1672 }
1673
1674 #define RV1126_PULL_PMU_OFFSET 0x40
1675 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1676 #define RV1126_PULL_PINS_PER_REG 8
1677 #define RV1126_PULL_BITS_PER_PIN 2
1678 #define RV1126_PULL_BANK_STRIDE 16
1679 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1680
rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1681 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1682 int pin_num, struct regmap **regmap,
1683 int *reg, u8 *bit)
1684 {
1685 struct rockchip_pinctrl *info = bank->drvdata;
1686
1687 /* The first 24 pins of the first bank are located in PMU */
1688 if (bank->bank_num == 0) {
1689 if (RV1126_GPIO_C4_D7(pin_num)) {
1690 *regmap = info->regmap_base;
1691 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1692 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1693 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1694 *bit *= RV1126_PULL_BITS_PER_PIN;
1695 return 0;
1696 }
1697 *regmap = info->regmap_pmu;
1698 *reg = RV1126_PULL_PMU_OFFSET;
1699 } else {
1700 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1701 *regmap = info->regmap_base;
1702 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1703 }
1704
1705 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1706 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1707 *bit *= RV1126_PULL_BITS_PER_PIN;
1708
1709 return 0;
1710 }
1711
1712 #define RV1126_DRV_PMU_OFFSET 0x20
1713 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1714 #define RV1126_DRV_BITS_PER_PIN 4
1715 #define RV1126_DRV_PINS_PER_REG 4
1716 #define RV1126_DRV_BANK_STRIDE 32
1717
rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1718 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1719 int pin_num, struct regmap **regmap,
1720 int *reg, u8 *bit)
1721 {
1722 struct rockchip_pinctrl *info = bank->drvdata;
1723
1724 /* The first 24 pins of the first bank are located in PMU */
1725 if (bank->bank_num == 0) {
1726 if (RV1126_GPIO_C4_D7(pin_num)) {
1727 *regmap = info->regmap_base;
1728 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1729 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1730 *reg -= 0x4;
1731 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1732 *bit *= RV1126_DRV_BITS_PER_PIN;
1733 return 0;
1734 }
1735 *regmap = info->regmap_pmu;
1736 *reg = RV1126_DRV_PMU_OFFSET;
1737 } else {
1738 *regmap = info->regmap_base;
1739 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1740 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1741 }
1742
1743 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1744 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1745 *bit *= RV1126_DRV_BITS_PER_PIN;
1746
1747 return 0;
1748 }
1749
1750 #define RV1126_SCHMITT_PMU_OFFSET 0x60
1751 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1752 #define RV1126_SCHMITT_BANK_STRIDE 16
1753 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1754 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1755
rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1756 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1757 int pin_num,
1758 struct regmap **regmap,
1759 int *reg, u8 *bit)
1760 {
1761 struct rockchip_pinctrl *info = bank->drvdata;
1762 int pins_per_reg;
1763
1764 if (bank->bank_num == 0) {
1765 if (RV1126_GPIO_C4_D7(pin_num)) {
1766 *regmap = info->regmap_base;
1767 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1768 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1769 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1770 return 0;
1771 }
1772 *regmap = info->regmap_pmu;
1773 *reg = RV1126_SCHMITT_PMU_OFFSET;
1774 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1775 } else {
1776 *regmap = info->regmap_base;
1777 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1778 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1779 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1780 }
1781 *reg += ((pin_num / pins_per_reg) * 4);
1782 *bit = pin_num % pins_per_reg;
1783
1784 return 0;
1785 }
1786
1787 #define RK3308_SCHMITT_PINS_PER_REG 8
1788 #define RK3308_SCHMITT_BANK_STRIDE 16
1789 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1790
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1791 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1792 int pin_num, struct regmap **regmap,
1793 int *reg, u8 *bit)
1794 {
1795 struct rockchip_pinctrl *info = bank->drvdata;
1796
1797 *regmap = info->regmap_base;
1798 *reg = RK3308_SCHMITT_GRF_OFFSET;
1799
1800 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1801 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1802 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1803
1804 return 0;
1805 }
1806
1807 #define RK1808_PULL_PMU_OFFSET 0x10
1808 #define RK1808_PULL_GRF_OFFSET 0x80
1809 #define RK1808_PULL_PINS_PER_REG 8
1810 #define RK1808_PULL_BITS_PER_PIN 2
1811 #define RK1808_PULL_BANK_STRIDE 16
1812
rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1813 static int rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1814 int pin_num, struct regmap **regmap,
1815 int *reg, u8 *bit)
1816 {
1817 struct rockchip_pinctrl *info = bank->drvdata;
1818
1819 if (bank->bank_num == 0) {
1820 *regmap = info->regmap_pmu;
1821 *reg = RK1808_PULL_PMU_OFFSET;
1822 } else {
1823 *reg = RK1808_PULL_GRF_OFFSET;
1824 *regmap = info->regmap_base;
1825 *reg += (bank->bank_num - 1) * RK1808_PULL_BANK_STRIDE;
1826 }
1827
1828 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
1829 *bit = (pin_num % RK1808_PULL_PINS_PER_REG);
1830 *bit *= RK1808_PULL_BITS_PER_PIN;
1831
1832 return 0;
1833 }
1834
1835 #define RK1808_DRV_PMU_OFFSET 0x20
1836 #define RK1808_DRV_GRF_OFFSET 0x140
1837 #define RK1808_DRV_BITS_PER_PIN 2
1838 #define RK1808_DRV_PINS_PER_REG 8
1839 #define RK1808_DRV_BANK_STRIDE 16
1840
rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1841 static int rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1842 int pin_num,
1843 struct regmap **regmap,
1844 int *reg, u8 *bit)
1845 {
1846 struct rockchip_pinctrl *info = bank->drvdata;
1847
1848 if (bank->bank_num == 0) {
1849 *regmap = info->regmap_pmu;
1850 *reg = RK1808_DRV_PMU_OFFSET;
1851 } else {
1852 *regmap = info->regmap_base;
1853 *reg = RK1808_DRV_GRF_OFFSET;
1854 *reg += (bank->bank_num - 1) * RK1808_DRV_BANK_STRIDE;
1855 }
1856
1857 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
1858 *bit = pin_num % RK1808_DRV_PINS_PER_REG;
1859 *bit *= RK1808_DRV_BITS_PER_PIN;
1860
1861 return 0;
1862 }
1863
1864 #define RK1808_SR_PMU_OFFSET 0x0030
1865 #define RK1808_SR_GRF_OFFSET 0x00c0
1866 #define RK1808_SR_BANK_STRIDE 16
1867 #define RK1808_SR_PINS_PER_REG 8
1868
rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1869 static int rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
1870 int pin_num,
1871 struct regmap **regmap,
1872 int *reg, u8 *bit)
1873 {
1874 struct rockchip_pinctrl *info = bank->drvdata;
1875
1876 if (bank->bank_num == 0) {
1877 *regmap = info->regmap_pmu;
1878 *reg = RK1808_SR_PMU_OFFSET;
1879 } else {
1880 *regmap = info->regmap_base;
1881 *reg = RK1808_SR_GRF_OFFSET;
1882 *reg += (bank->bank_num - 1) * RK1808_SR_BANK_STRIDE;
1883 }
1884 *reg += ((pin_num / RK1808_SR_PINS_PER_REG) * 4);
1885 *bit = pin_num % RK1808_SR_PINS_PER_REG;
1886
1887 return 0;
1888 }
1889
1890 #define RK1808_SCHMITT_PMU_OFFSET 0x0040
1891 #define RK1808_SCHMITT_GRF_OFFSET 0x0100
1892 #define RK1808_SCHMITT_BANK_STRIDE 16
1893 #define RK1808_SCHMITT_PINS_PER_REG 8
1894
rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1895 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1896 int pin_num,
1897 struct regmap **regmap,
1898 int *reg, u8 *bit)
1899 {
1900 struct rockchip_pinctrl *info = bank->drvdata;
1901
1902 if (bank->bank_num == 0) {
1903 *regmap = info->regmap_pmu;
1904 *reg = RK1808_SCHMITT_PMU_OFFSET;
1905 } else {
1906 *regmap = info->regmap_base;
1907 *reg = RK1808_SCHMITT_GRF_OFFSET;
1908 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE;
1909 }
1910 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
1911 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
1912
1913 return 0;
1914 }
1915
1916 #define RK2928_PULL_OFFSET 0x118
1917 #define RK2928_PULL_PINS_PER_REG 16
1918 #define RK2928_PULL_BANK_STRIDE 8
1919
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1920 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1921 int pin_num, struct regmap **regmap,
1922 int *reg, u8 *bit)
1923 {
1924 struct rockchip_pinctrl *info = bank->drvdata;
1925
1926 *regmap = info->regmap_base;
1927 *reg = RK2928_PULL_OFFSET;
1928 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1929 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1930
1931 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1932
1933 return 0;
1934 };
1935
1936 #define RK3128_PULL_OFFSET 0x118
1937
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1938 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1939 int pin_num, struct regmap **regmap,
1940 int *reg, u8 *bit)
1941 {
1942 struct rockchip_pinctrl *info = bank->drvdata;
1943
1944 *regmap = info->regmap_base;
1945 *reg = RK3128_PULL_OFFSET;
1946 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1947 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1948
1949 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1950
1951 return 0;
1952 }
1953
1954 #define RK3188_PULL_OFFSET 0x164
1955 #define RK3188_PULL_BITS_PER_PIN 2
1956 #define RK3188_PULL_PINS_PER_REG 8
1957 #define RK3188_PULL_BANK_STRIDE 16
1958 #define RK3188_PULL_PMU_OFFSET 0x64
1959
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1960 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1961 int pin_num, struct regmap **regmap,
1962 int *reg, u8 *bit)
1963 {
1964 struct rockchip_pinctrl *info = bank->drvdata;
1965
1966 /* The first 12 pins of the first bank are located elsewhere */
1967 if (bank->bank_num == 0 && pin_num < 12) {
1968 *regmap = info->regmap_pmu ? info->regmap_pmu
1969 : bank->regmap_pull;
1970 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1971 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1972 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1973 *bit *= RK3188_PULL_BITS_PER_PIN;
1974 } else {
1975 *regmap = info->regmap_pull ? info->regmap_pull
1976 : info->regmap_base;
1977 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1978
1979 /* correct the offset, as it is the 2nd pull register */
1980 *reg -= 4;
1981 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1982 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1983
1984 /*
1985 * The bits in these registers have an inverse ordering
1986 * with the lowest pin being in bits 15:14 and the highest
1987 * pin in bits 1:0
1988 */
1989 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1990 *bit *= RK3188_PULL_BITS_PER_PIN;
1991 }
1992
1993 return 0;
1994 }
1995
1996 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1997 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1998 int pin_num, struct regmap **regmap,
1999 int *reg, u8 *bit)
2000 {
2001 struct rockchip_pinctrl *info = bank->drvdata;
2002
2003 /* The first 24 pins of the first bank are located in PMU */
2004 if (bank->bank_num == 0) {
2005 *regmap = info->regmap_pmu;
2006 *reg = RK3188_PULL_PMU_OFFSET;
2007
2008 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2009 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2010 *bit *= RK3188_PULL_BITS_PER_PIN;
2011 } else {
2012 *regmap = info->regmap_base;
2013 *reg = RK3288_PULL_OFFSET;
2014
2015 /* correct the offset, as we're starting with the 2nd bank */
2016 *reg -= 0x10;
2017 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2018 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2019
2020 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2021 *bit *= RK3188_PULL_BITS_PER_PIN;
2022 }
2023
2024 return 0;
2025 }
2026
2027 #define RK3288_DRV_PMU_OFFSET 0x70
2028 #define RK3288_DRV_GRF_OFFSET 0x1c0
2029 #define RK3288_DRV_BITS_PER_PIN 2
2030 #define RK3288_DRV_PINS_PER_REG 8
2031 #define RK3288_DRV_BANK_STRIDE 16
2032
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2033 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2034 int pin_num, struct regmap **regmap,
2035 int *reg, u8 *bit)
2036 {
2037 struct rockchip_pinctrl *info = bank->drvdata;
2038
2039 /* The first 24 pins of the first bank are located in PMU */
2040 if (bank->bank_num == 0) {
2041 *regmap = info->regmap_pmu;
2042 *reg = RK3288_DRV_PMU_OFFSET;
2043
2044 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2045 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2046 *bit *= RK3288_DRV_BITS_PER_PIN;
2047 } else {
2048 *regmap = info->regmap_base;
2049 *reg = RK3288_DRV_GRF_OFFSET;
2050
2051 /* correct the offset, as we're starting with the 2nd bank */
2052 *reg -= 0x10;
2053 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2054 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2055
2056 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2057 *bit *= RK3288_DRV_BITS_PER_PIN;
2058 }
2059
2060 return 0;
2061 }
2062
2063 #define RK3228_PULL_OFFSET 0x100
2064
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2065 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2066 int pin_num, struct regmap **regmap,
2067 int *reg, u8 *bit)
2068 {
2069 struct rockchip_pinctrl *info = bank->drvdata;
2070
2071 *regmap = info->regmap_base;
2072 *reg = RK3228_PULL_OFFSET;
2073 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2074 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2075
2076 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2077 *bit *= RK3188_PULL_BITS_PER_PIN;
2078
2079 return 0;
2080 }
2081
2082 #define RK3228_DRV_GRF_OFFSET 0x200
2083
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2084 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2085 int pin_num, struct regmap **regmap,
2086 int *reg, u8 *bit)
2087 {
2088 struct rockchip_pinctrl *info = bank->drvdata;
2089
2090 *regmap = info->regmap_base;
2091 *reg = RK3228_DRV_GRF_OFFSET;
2092 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2093 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2094
2095 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2096 *bit *= RK3288_DRV_BITS_PER_PIN;
2097
2098 return 0;
2099 }
2100
2101 #define RK3308_PULL_OFFSET 0xa0
2102
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2103 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2104 int pin_num, struct regmap **regmap,
2105 int *reg, u8 *bit)
2106 {
2107 struct rockchip_pinctrl *info = bank->drvdata;
2108
2109 *regmap = info->regmap_base;
2110 *reg = RK3308_PULL_OFFSET;
2111 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2112 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2113
2114 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2115 *bit *= RK3188_PULL_BITS_PER_PIN;
2116
2117 return 0;
2118 }
2119
2120 #define RK3308_DRV_GRF_OFFSET 0x100
2121
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2122 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2123 int pin_num, struct regmap **regmap,
2124 int *reg, u8 *bit)
2125 {
2126 struct rockchip_pinctrl *info = bank->drvdata;
2127
2128 *regmap = info->regmap_base;
2129 *reg = RK3308_DRV_GRF_OFFSET;
2130 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2131 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2132
2133 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2134 *bit *= RK3288_DRV_BITS_PER_PIN;
2135
2136 return 0;
2137 }
2138
2139 #define RK3308_SLEW_RATE_GRF_OFFSET 0x150
2140 #define RK3308_SLEW_RATE_BANK_STRIDE 16
2141 #define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
2142
rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2143 static int rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
2144 int pin_num,
2145 struct regmap **regmap,
2146 int *reg, u8 *bit)
2147 {
2148 struct rockchip_pinctrl *info = bank->drvdata;
2149 int pins_per_reg;
2150
2151 *regmap = info->regmap_base;
2152 *reg = RK3308_SLEW_RATE_GRF_OFFSET;
2153 *reg += (bank->bank_num) * RK3308_SLEW_RATE_BANK_STRIDE;
2154 pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
2155
2156 *reg += ((pin_num / pins_per_reg) * 4);
2157 *bit = pin_num % pins_per_reg;
2158
2159 return 0;
2160 }
2161
2162 #define RK3368_PULL_GRF_OFFSET 0x100
2163 #define RK3368_PULL_PMU_OFFSET 0x10
2164
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2165 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2166 int pin_num, struct regmap **regmap,
2167 int *reg, u8 *bit)
2168 {
2169 struct rockchip_pinctrl *info = bank->drvdata;
2170
2171 /* The first 32 pins of the first bank are located in PMU */
2172 if (bank->bank_num == 0) {
2173 *regmap = info->regmap_pmu;
2174 *reg = RK3368_PULL_PMU_OFFSET;
2175
2176 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2177 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2178 *bit *= RK3188_PULL_BITS_PER_PIN;
2179 } else {
2180 *regmap = info->regmap_base;
2181 *reg = RK3368_PULL_GRF_OFFSET;
2182
2183 /* correct the offset, as we're starting with the 2nd bank */
2184 *reg -= 0x10;
2185 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2186 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2187
2188 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2189 *bit *= RK3188_PULL_BITS_PER_PIN;
2190 }
2191
2192 return 0;
2193 }
2194
2195 #define RK3368_DRV_PMU_OFFSET 0x20
2196 #define RK3368_DRV_GRF_OFFSET 0x200
2197
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2198 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2199 int pin_num, struct regmap **regmap,
2200 int *reg, u8 *bit)
2201 {
2202 struct rockchip_pinctrl *info = bank->drvdata;
2203
2204 /* The first 32 pins of the first bank are located in PMU */
2205 if (bank->bank_num == 0) {
2206 *regmap = info->regmap_pmu;
2207 *reg = RK3368_DRV_PMU_OFFSET;
2208
2209 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2210 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2211 *bit *= RK3288_DRV_BITS_PER_PIN;
2212 } else {
2213 *regmap = info->regmap_base;
2214 *reg = RK3368_DRV_GRF_OFFSET;
2215
2216 /* correct the offset, as we're starting with the 2nd bank */
2217 *reg -= 0x10;
2218 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2219 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2220
2221 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2222 *bit *= RK3288_DRV_BITS_PER_PIN;
2223 }
2224
2225 return 0;
2226 }
2227
2228 #define RK3399_PULL_GRF_OFFSET 0xe040
2229 #define RK3399_PULL_PMU_OFFSET 0x40
2230 #define RK3399_DRV_3BITS_PER_PIN 3
2231
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2232 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2233 int pin_num, struct regmap **regmap,
2234 int *reg, u8 *bit)
2235 {
2236 struct rockchip_pinctrl *info = bank->drvdata;
2237
2238 /* The bank0:16 and bank1:32 pins are located in PMU */
2239 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2240 *regmap = info->regmap_pmu;
2241 *reg = RK3399_PULL_PMU_OFFSET;
2242
2243 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2244
2245 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2246 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2247 *bit *= RK3188_PULL_BITS_PER_PIN;
2248 } else {
2249 *regmap = info->regmap_base;
2250 *reg = RK3399_PULL_GRF_OFFSET;
2251
2252 /* correct the offset, as we're starting with the 3rd bank */
2253 *reg -= 0x20;
2254 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2255 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2256
2257 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2258 *bit *= RK3188_PULL_BITS_PER_PIN;
2259 }
2260
2261 return 0;
2262 }
2263
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2264 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2265 int pin_num, struct regmap **regmap,
2266 int *reg, u8 *bit)
2267 {
2268 struct rockchip_pinctrl *info = bank->drvdata;
2269 int drv_num = (pin_num / 8);
2270
2271 /* The bank0:16 and bank1:32 pins are located in PMU */
2272 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2273 *regmap = info->regmap_pmu;
2274 else
2275 *regmap = info->regmap_base;
2276
2277 *reg = bank->drv[drv_num].offset;
2278 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2279 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2280 *bit = (pin_num % 8) * 3;
2281 else
2282 *bit = (pin_num % 8) * 2;
2283
2284 return 0;
2285 }
2286
2287 #define RK3528_DRV_BITS_PER_PIN 8
2288 #define RK3528_DRV_PINS_PER_REG 2
2289 #define RK3528_DRV_GPIO0_OFFSET 0x100
2290 #define RK3528_DRV_GPIO1_OFFSET 0x20120
2291 #define RK3528_DRV_GPIO2_OFFSET 0x30160
2292 #define RK3528_DRV_GPIO3_OFFSET 0x20190
2293 #define RK3528_DRV_GPIO4_OFFSET 0x101C0
2294
rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2295 static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2296 int pin_num, struct regmap **regmap,
2297 int *reg, u8 *bit)
2298 {
2299 struct rockchip_pinctrl *info = bank->drvdata;
2300
2301 *regmap = info->regmap_base;
2302 switch (bank->bank_num) {
2303 case 0:
2304 *reg = RK3528_DRV_GPIO0_OFFSET;
2305 break;
2306
2307 case 1:
2308 *reg = RK3528_DRV_GPIO1_OFFSET;
2309 break;
2310
2311 case 2:
2312 *reg = RK3528_DRV_GPIO2_OFFSET;
2313 break;
2314
2315 case 3:
2316 *reg = RK3528_DRV_GPIO3_OFFSET;
2317 break;
2318
2319 case 4:
2320 *reg = RK3528_DRV_GPIO4_OFFSET;
2321 break;
2322
2323 default:
2324 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2325 break;
2326 }
2327
2328 *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
2329 *bit = pin_num % RK3528_DRV_PINS_PER_REG;
2330 *bit *= RK3528_DRV_BITS_PER_PIN;
2331
2332 return 0;
2333 }
2334
2335 #define RK3528_PULL_BITS_PER_PIN 2
2336 #define RK3528_PULL_PINS_PER_REG 8
2337 #define RK3528_PULL_GPIO0_OFFSET 0x200
2338 #define RK3528_PULL_GPIO1_OFFSET 0x20210
2339 #define RK3528_PULL_GPIO2_OFFSET 0x30220
2340 #define RK3528_PULL_GPIO3_OFFSET 0x20230
2341 #define RK3528_PULL_GPIO4_OFFSET 0x10240
2342
rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2343 static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2344 int pin_num, struct regmap **regmap,
2345 int *reg, u8 *bit)
2346 {
2347 struct rockchip_pinctrl *info = bank->drvdata;
2348
2349 *regmap = info->regmap_base;
2350 switch (bank->bank_num) {
2351 case 0:
2352 *reg = RK3528_PULL_GPIO0_OFFSET;
2353 break;
2354
2355 case 1:
2356 *reg = RK3528_PULL_GPIO1_OFFSET;
2357 break;
2358
2359 case 2:
2360 *reg = RK3528_PULL_GPIO2_OFFSET;
2361 break;
2362
2363 case 3:
2364 *reg = RK3528_PULL_GPIO3_OFFSET;
2365 break;
2366
2367 case 4:
2368 *reg = RK3528_PULL_GPIO4_OFFSET;
2369 break;
2370
2371 default:
2372 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2373 break;
2374 }
2375
2376 *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
2377 *bit = pin_num % RK3528_PULL_PINS_PER_REG;
2378 *bit *= RK3528_PULL_BITS_PER_PIN;
2379
2380 return 0;
2381 }
2382
2383 #define RK3528_SMT_BITS_PER_PIN 1
2384 #define RK3528_SMT_PINS_PER_REG 8
2385 #define RK3528_SMT_GPIO0_OFFSET 0x400
2386 #define RK3528_SMT_GPIO1_OFFSET 0x20410
2387 #define RK3528_SMT_GPIO2_OFFSET 0x30420
2388 #define RK3528_SMT_GPIO3_OFFSET 0x20430
2389 #define RK3528_SMT_GPIO4_OFFSET 0x10440
2390
rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2391 static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2392 int pin_num,
2393 struct regmap **regmap,
2394 int *reg, u8 *bit)
2395 {
2396 struct rockchip_pinctrl *info = bank->drvdata;
2397
2398 *regmap = info->regmap_base;
2399 switch (bank->bank_num) {
2400 case 0:
2401 *reg = RK3528_SMT_GPIO0_OFFSET;
2402 break;
2403
2404 case 1:
2405 *reg = RK3528_SMT_GPIO1_OFFSET;
2406 break;
2407
2408 case 2:
2409 *reg = RK3528_SMT_GPIO2_OFFSET;
2410 break;
2411
2412 case 3:
2413 *reg = RK3528_SMT_GPIO3_OFFSET;
2414 break;
2415
2416 case 4:
2417 *reg = RK3528_SMT_GPIO4_OFFSET;
2418 break;
2419
2420 default:
2421 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2422 break;
2423 }
2424
2425 *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
2426 *bit = pin_num % RK3528_SMT_PINS_PER_REG;
2427 *bit *= RK3528_SMT_BITS_PER_PIN;
2428 return 0;
2429 }
2430
2431 #define RK3562_DRV_BITS_PER_PIN 8
2432 #define RK3562_DRV_PINS_PER_REG 2
2433 #define RK3562_DRV_GPIO0_OFFSET 0x20070
2434 #define RK3562_DRV_GPIO1_OFFSET 0x200
2435 #define RK3562_DRV_GPIO2_OFFSET 0x240
2436 #define RK3562_DRV_GPIO3_OFFSET 0x10280
2437 #define RK3562_DRV_GPIO4_OFFSET 0x102C0
2438
rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2439 static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2440 int pin_num, struct regmap **regmap,
2441 int *reg, u8 *bit)
2442 {
2443 struct rockchip_pinctrl *info = bank->drvdata;
2444
2445 *regmap = info->regmap_base;
2446 switch (bank->bank_num) {
2447 case 0:
2448 *reg = RK3562_DRV_GPIO0_OFFSET;
2449 break;
2450
2451 case 1:
2452 *reg = RK3562_DRV_GPIO1_OFFSET;
2453 break;
2454
2455 case 2:
2456 *reg = RK3562_DRV_GPIO2_OFFSET;
2457 break;
2458
2459 case 3:
2460 *reg = RK3562_DRV_GPIO3_OFFSET;
2461 break;
2462
2463 case 4:
2464 *reg = RK3562_DRV_GPIO4_OFFSET;
2465 break;
2466
2467 default:
2468 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2469 break;
2470 }
2471
2472 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
2473 *bit = pin_num % RK3562_DRV_PINS_PER_REG;
2474 *bit *= RK3562_DRV_BITS_PER_PIN;
2475
2476 return 0;
2477 }
2478
2479 #define RK3562_PULL_BITS_PER_PIN 2
2480 #define RK3562_PULL_PINS_PER_REG 8
2481 #define RK3562_PULL_GPIO0_OFFSET 0x20020
2482 #define RK3562_PULL_GPIO1_OFFSET 0x80
2483 #define RK3562_PULL_GPIO2_OFFSET 0x90
2484 #define RK3562_PULL_GPIO3_OFFSET 0x100A0
2485 #define RK3562_PULL_GPIO4_OFFSET 0x100B0
2486
rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2487 static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2488 int pin_num, struct regmap **regmap,
2489 int *reg, u8 *bit)
2490 {
2491 struct rockchip_pinctrl *info = bank->drvdata;
2492
2493 *regmap = info->regmap_base;
2494 switch (bank->bank_num) {
2495 case 0:
2496 *reg = RK3562_PULL_GPIO0_OFFSET;
2497 break;
2498
2499 case 1:
2500 *reg = RK3562_PULL_GPIO1_OFFSET;
2501 break;
2502
2503 case 2:
2504 *reg = RK3562_PULL_GPIO2_OFFSET;
2505 break;
2506
2507 case 3:
2508 *reg = RK3562_PULL_GPIO3_OFFSET;
2509 break;
2510
2511 case 4:
2512 *reg = RK3562_PULL_GPIO4_OFFSET;
2513 break;
2514
2515 default:
2516 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2517 break;
2518 }
2519
2520 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
2521 *bit = pin_num % RK3562_PULL_PINS_PER_REG;
2522 *bit *= RK3562_PULL_BITS_PER_PIN;
2523
2524 return 0;
2525 }
2526
2527 #define RK3562_SMT_BITS_PER_PIN 2
2528 #define RK3562_SMT_PINS_PER_REG 8
2529 #define RK3562_SMT_GPIO0_OFFSET 0x20030
2530 #define RK3562_SMT_GPIO1_OFFSET 0xC0
2531 #define RK3562_SMT_GPIO2_OFFSET 0xD0
2532 #define RK3562_SMT_GPIO3_OFFSET 0x100E0
2533 #define RK3562_SMT_GPIO4_OFFSET 0x100F0
2534
rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2535 static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2536 int pin_num,
2537 struct regmap **regmap,
2538 int *reg, u8 *bit)
2539 {
2540 struct rockchip_pinctrl *info = bank->drvdata;
2541
2542 *regmap = info->regmap_base;
2543 switch (bank->bank_num) {
2544 case 0:
2545 *reg = RK3562_SMT_GPIO0_OFFSET;
2546 break;
2547
2548 case 1:
2549 *reg = RK3562_SMT_GPIO1_OFFSET;
2550 break;
2551
2552 case 2:
2553 *reg = RK3562_SMT_GPIO2_OFFSET;
2554 break;
2555
2556 case 3:
2557 *reg = RK3562_SMT_GPIO3_OFFSET;
2558 break;
2559
2560 case 4:
2561 *reg = RK3562_SMT_GPIO4_OFFSET;
2562 break;
2563
2564 default:
2565 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2566 break;
2567 }
2568
2569 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
2570 *bit = pin_num % RK3562_SMT_PINS_PER_REG;
2571 *bit *= RK3562_SMT_BITS_PER_PIN;
2572
2573 return 0;
2574 }
2575
2576 #define RK3568_SR_PMU_OFFSET 0x60
2577 #define RK3568_SR_GRF_OFFSET 0x0180
2578 #define RK3568_SR_BANK_STRIDE 0x10
2579 #define RK3568_SR_BITS_PER_PIN 2
2580 #define RK3568_SR_PINS_PER_REG 8
2581
rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2582 static int rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
2583 int pin_num,
2584 struct regmap **regmap,
2585 int *reg, u8 *bit)
2586 {
2587 struct rockchip_pinctrl *info = bank->drvdata;
2588
2589 if (bank->bank_num == 0) {
2590 *regmap = info->regmap_pmu;
2591 *reg = RK3568_SR_PMU_OFFSET;
2592 } else {
2593 *regmap = info->regmap_base;
2594 *reg = RK3568_SR_GRF_OFFSET;
2595 *reg += (bank->bank_num - 1) * RK3568_SR_BANK_STRIDE;
2596 }
2597 *reg += ((pin_num / RK3568_SR_PINS_PER_REG) * 4);
2598 *bit = pin_num % RK3568_SR_PINS_PER_REG;
2599 *bit *= RK3568_SR_BITS_PER_PIN;
2600
2601 return 0;
2602 }
2603
2604 #define RK3568_PULL_PMU_OFFSET 0x20
2605 #define RK3568_PULL_GRF_OFFSET 0x80
2606 #define RK3568_PULL_BITS_PER_PIN 2
2607 #define RK3568_PULL_PINS_PER_REG 8
2608 #define RK3568_PULL_BANK_STRIDE 0x10
2609
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2610 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2611 int pin_num, struct regmap **regmap,
2612 int *reg, u8 *bit)
2613 {
2614 struct rockchip_pinctrl *info = bank->drvdata;
2615
2616 if (bank->bank_num == 0) {
2617 *regmap = info->regmap_pmu;
2618 *reg = RK3568_PULL_PMU_OFFSET;
2619 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2620 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2621
2622 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
2623 *bit *= RK3568_PULL_BITS_PER_PIN;
2624 } else {
2625 *regmap = info->regmap_base;
2626 *reg = RK3568_PULL_GRF_OFFSET;
2627 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2628 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2629
2630 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2631 *bit *= RK3568_PULL_BITS_PER_PIN;
2632 }
2633
2634 return 0;
2635 }
2636
2637 #define RK3568_DRV_PMU_OFFSET 0x70
2638 #define RK3568_DRV_GRF_OFFSET 0x200
2639 #define RK3568_DRV_BITS_PER_PIN 8
2640 #define RK3568_DRV_PINS_PER_REG 2
2641 #define RK3568_DRV_BANK_STRIDE 0x40
2642
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2643 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2644 int pin_num, struct regmap **regmap,
2645 int *reg, u8 *bit)
2646 {
2647 struct rockchip_pinctrl *info = bank->drvdata;
2648
2649 /* The first 32 pins of the first bank are located in PMU */
2650 if (bank->bank_num == 0) {
2651 *regmap = info->regmap_pmu;
2652 *reg = RK3568_DRV_PMU_OFFSET;
2653 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2654
2655 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
2656 *bit *= RK3568_DRV_BITS_PER_PIN;
2657 } else {
2658 *regmap = info->regmap_base;
2659 *reg = RK3568_DRV_GRF_OFFSET;
2660 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2661 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2662
2663 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2664 *bit *= RK3568_DRV_BITS_PER_PIN;
2665 }
2666
2667 if (rockchip_get_cpu_version() == 0)
2668 if ((bank->bank_num == 1 && (pin_num == 15 || pin_num == 23 || pin_num == 31)) ||
2669 ((bank->bank_num == 2 || bank->bank_num == 3 || bank->bank_num == 4) &&
2670 (pin_num == 7 || pin_num == 15 || pin_num == 23 || pin_num == 31)))
2671 *bit -= RK3568_DRV_BITS_PER_PIN;
2672
2673 return 0;
2674 }
2675
2676 #define RK3588_PMU1_IOC_REG (0x0000)
2677 #define RK3588_PMU2_IOC_REG (0x4000)
2678 #define RK3588_BUS_IOC_REG (0x8000)
2679 #define RK3588_VCCIO1_4_IOC_REG (0x9000)
2680 #define RK3588_VCCIO3_5_IOC_REG (0xA000)
2681 #define RK3588_VCCIO2_IOC_REG (0xB000)
2682 #define RK3588_VCCIO6_IOC_REG (0xC000)
2683 #define RK3588_EMMC_IOC_REG (0xD000)
2684
2685 static const u32 rk3588_ds_regs[][2] = {
2686 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2687 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2688 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2689 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2690 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2691 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2692 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2693 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2694 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2695 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2696 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2697 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2698 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2699 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2700 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2701 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2702 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2703 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2704 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2705 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2706 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2707 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2708 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2709 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2710 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2711 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2712 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2713 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2714 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2715 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2716 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2717 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2718 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2719 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2720 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2721 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2722 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2723 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2724 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2725 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2726 };
2727
2728 static const u32 rk3588_p_regs[][2] = {
2729 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2730 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2731 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2732 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2733 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2734 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2735 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2736 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2737 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2738 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2739 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2740 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2741 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2742 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2743 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2744 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2745 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2746 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2747 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2748 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2749 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2750 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2751 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2752 };
2753
2754 static const u32 rk3588_smt_regs[][2] = {
2755 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2756 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2757 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2758 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2759 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2760 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2761 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2762 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2763 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2764 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2765 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2766 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2767 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2768 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2769 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2770 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2771 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2772 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2773 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2774 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2775 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2776 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2777 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2778 };
2779
2780 #define RK3588_PULL_BITS_PER_PIN 2
2781 #define RK3588_PULL_PINS_PER_REG 8
2782
rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2783 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2784 int pin_num, struct regmap **regmap,
2785 int *reg, u8 *bit)
2786 {
2787 struct rockchip_pinctrl *info = bank->drvdata;
2788 u8 bank_num = bank->bank_num;
2789 u32 pin = bank_num * 32 + pin_num;
2790 int i;
2791
2792 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2793 if (pin >= rk3588_p_regs[i][0]) {
2794 *reg = rk3588_p_regs[i][1];
2795 break;
2796 }
2797 BUG_ON(i == 0);
2798 }
2799
2800 *regmap = info->regmap_base;
2801 *reg += ((pin - rk3588_p_regs[i][0]) / RK3588_PULL_PINS_PER_REG) * 4;
2802 *bit = pin_num % RK3588_PULL_PINS_PER_REG;
2803 *bit *= RK3588_PULL_BITS_PER_PIN;
2804
2805 return 0;
2806 }
2807
2808 #define RK3588_DRV_BITS_PER_PIN 4
2809 #define RK3588_DRV_PINS_PER_REG 4
2810
rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2811 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2812 int pin_num, struct regmap **regmap,
2813 int *reg, u8 *bit)
2814 {
2815 struct rockchip_pinctrl *info = bank->drvdata;
2816 u8 bank_num = bank->bank_num;
2817 u32 pin = bank_num * 32 + pin_num;
2818 int i;
2819
2820 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2821 if (pin >= rk3588_ds_regs[i][0]) {
2822 *reg = rk3588_ds_regs[i][1];
2823 break;
2824 }
2825 BUG_ON(i == 0);
2826 }
2827
2828 *regmap = info->regmap_base;
2829 *reg += ((pin - rk3588_ds_regs[i][0]) / RK3588_DRV_PINS_PER_REG) * 4;
2830 *bit = pin_num % RK3588_DRV_PINS_PER_REG;
2831 *bit *= RK3588_DRV_BITS_PER_PIN;
2832
2833 return 0;
2834 }
2835
2836 #define RK3588_SMT_BITS_PER_PIN 1
2837 #define RK3588_SMT_PINS_PER_REG 8
2838
rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2839 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2840 int pin_num,
2841 struct regmap **regmap,
2842 int *reg, u8 *bit)
2843 {
2844 struct rockchip_pinctrl *info = bank->drvdata;
2845 u8 bank_num = bank->bank_num;
2846 u32 pin = bank_num * 32 + pin_num;
2847 int i;
2848
2849 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2850 if (pin >= rk3588_smt_regs[i][0]) {
2851 *reg = rk3588_smt_regs[i][1];
2852 break;
2853 }
2854 BUG_ON(i == 0);
2855 }
2856
2857 *regmap = info->regmap_base;
2858 *reg += ((pin - rk3588_smt_regs[i][0]) / RK3588_SMT_PINS_PER_REG) * 4;
2859 *bit = pin_num % RK3588_SMT_PINS_PER_REG;
2860 *bit *= RK3588_SMT_BITS_PER_PIN;
2861
2862 return 0;
2863 }
2864
2865 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2866 { 2, 4, 8, 12, -1, -1, -1, -1 },
2867 { 3, 6, 9, 12, -1, -1, -1, -1 },
2868 { 5, 10, 15, 20, -1, -1, -1, -1 },
2869 { 4, 6, 8, 10, 12, 14, 16, 18 },
2870 { 4, 7, 10, 13, 16, 19, 22, 26 },
2871 { 0, 2, 4, 6, 6, 8, 10, 12 }
2872 };
2873
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)2874 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2875 int pin_num)
2876 {
2877 struct rockchip_pinctrl *info = bank->drvdata;
2878 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2879 struct device *dev = info->dev;
2880 struct regmap *regmap;
2881 int reg, ret;
2882 u32 data, temp, rmask_bits;
2883 u8 bit;
2884 int drv_type = bank->drv[pin_num / 8].drv_type;
2885
2886 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2887 if (ret)
2888 return ret;
2889
2890 switch (drv_type) {
2891 case DRV_TYPE_IO_1V8_3V0_AUTO:
2892 case DRV_TYPE_IO_3V3_ONLY:
2893 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2894 switch (bit) {
2895 case 0 ... 12:
2896 /* regular case, nothing to do */
2897 break;
2898 case 15:
2899 /*
2900 * drive-strength offset is special, as it is
2901 * spread over 2 registers
2902 */
2903 ret = regmap_read(regmap, reg, &data);
2904 if (ret)
2905 return ret;
2906
2907 ret = regmap_read(regmap, reg + 0x4, &temp);
2908 if (ret)
2909 return ret;
2910
2911 /*
2912 * the bit data[15] contains bit 0 of the value
2913 * while temp[1:0] contains bits 2 and 1
2914 */
2915 data >>= 15;
2916 temp &= 0x3;
2917 temp <<= 1;
2918 data |= temp;
2919
2920 return rockchip_perpin_drv_list[drv_type][data];
2921 case 18 ... 21:
2922 /* setting fully enclosed in the second register */
2923 reg += 4;
2924 bit -= 16;
2925 break;
2926 default:
2927 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2928 bit, drv_type);
2929 return -EINVAL;
2930 }
2931
2932 break;
2933 case DRV_TYPE_IO_DEFAULT:
2934 case DRV_TYPE_IO_1V8_OR_3V0:
2935 case DRV_TYPE_IO_1V8_ONLY:
2936 case DRV_TYPE_IO_SMIC:
2937 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2938 break;
2939 default:
2940 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2941 return -EINVAL;
2942 }
2943
2944 ret = regmap_read(regmap, reg, &data);
2945 if (ret)
2946 return ret;
2947
2948 data >>= bit;
2949 data &= (1 << rmask_bits) - 1;
2950
2951 if (drv_type == DRV_TYPE_IO_SMIC) {
2952 u32 tmp = 0;
2953
2954 ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
2955 ret = regmap_read(regmap, reg, &tmp);
2956 if (ret)
2957 return ret;
2958
2959 tmp >>= bit;
2960 tmp &= 0x1;
2961
2962 data |= tmp << 2;
2963 }
2964
2965 return rockchip_perpin_drv_list[drv_type][data];
2966 }
2967
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)2968 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2969 int pin_num, int strength)
2970 {
2971 struct rockchip_pinctrl *info = bank->drvdata;
2972 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2973 struct device *dev = info->dev;
2974 struct regmap *regmap;
2975 int reg, ret, i, err;
2976 u32 data, rmask, rmask_bits, temp;
2977 u8 bit;
2978 int drv_type = bank->drv[pin_num / 8].drv_type;
2979
2980 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2981 bank->bank_num, pin_num, strength);
2982
2983 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2984 if (ret)
2985 return ret;
2986
2987 if (ctrl->type == RV1126 || ctrl->type == RK3588) {
2988 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2989 ret = strength;
2990 goto config;
2991 } else if (ctrl->type == RV1106 ||
2992 ctrl->type == RK3528 ||
2993 ctrl->type == RK3562 ||
2994 ctrl->type == RK3568) {
2995 rmask_bits = RK3568_DRV_BITS_PER_PIN;
2996 ret = (1 << (strength + 1)) - 1;
2997 goto config;
2998 }
2999
3000 ret = -EINVAL;
3001 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
3002 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
3003 ret = i;
3004 break;
3005 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
3006 ret = rockchip_perpin_drv_list[drv_type][i];
3007 break;
3008 }
3009 }
3010
3011 if (ret < 0) {
3012 dev_err(dev, "unsupported driver strength %d\n", strength);
3013 return ret;
3014 }
3015
3016 switch (drv_type) {
3017 case DRV_TYPE_IO_1V8_3V0_AUTO:
3018 case DRV_TYPE_IO_3V3_ONLY:
3019 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
3020 switch (bit) {
3021 case 0 ... 12:
3022 /* regular case, nothing to do */
3023 break;
3024 case 15:
3025 /*
3026 * drive-strength offset is special, as it is spread
3027 * over 2 registers, the bit data[15] contains bit 0
3028 * of the value while temp[1:0] contains bits 2 and 1
3029 */
3030 data = (ret & 0x1) << 15;
3031 temp = (ret >> 0x1) & 0x3;
3032
3033 rmask = BIT(15) | BIT(31);
3034 data |= BIT(31);
3035 err = regmap_update_bits(regmap, reg, rmask, data);
3036 if (err)
3037 return err;
3038
3039 rmask = 0x3 | (0x3 << 16);
3040 temp |= (0x3 << 16);
3041 reg += 0x4;
3042 err = regmap_update_bits(regmap, reg, rmask, temp);
3043
3044 return err;
3045 case 18 ... 21:
3046 /* setting fully enclosed in the second register */
3047 reg += 4;
3048 bit -= 16;
3049 break;
3050 default:
3051 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
3052 bit, drv_type);
3053 return -EINVAL;
3054 }
3055 break;
3056 case DRV_TYPE_IO_DEFAULT:
3057 case DRV_TYPE_IO_1V8_OR_3V0:
3058 case DRV_TYPE_IO_1V8_ONLY:
3059 case DRV_TYPE_IO_SMIC:
3060 rmask_bits = RK3288_DRV_BITS_PER_PIN;
3061 break;
3062 default:
3063 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
3064 return -EINVAL;
3065 }
3066
3067 config:
3068 /* enable the write to the equivalent lower bits */
3069 data = ((1 << rmask_bits) - 1) << (bit + 16);
3070 rmask = data | (data >> 16);
3071 data |= (ret << bit);
3072
3073 err = regmap_update_bits(regmap, reg, rmask, data);
3074 if (err)
3075 return err;
3076
3077 if (ctrl->type == RK3568 && rockchip_get_cpu_version() == 0) {
3078 if (bank->bank_num == 1 && pin_num == 21)
3079 reg = 0x0840;
3080 else if (bank->bank_num == 2 && pin_num == 2)
3081 reg = 0x0844;
3082 else if (bank->bank_num == 2 && pin_num == 8)
3083 reg = 0x0848;
3084 else if (bank->bank_num == 3 && pin_num == 0)
3085 reg = 0x084c;
3086 else if (bank->bank_num == 3 && pin_num == 6)
3087 reg = 0x0850;
3088 else if (bank->bank_num == 4 && pin_num == 0)
3089 reg = 0x0854;
3090 else
3091 return 0;
3092
3093 data = ((1 << rmask_bits) - 1) << 16;
3094 rmask = data | (data >> 16);
3095 data |= (1 << (strength + 1)) - 1;
3096
3097 err = regmap_update_bits(regmap, reg, rmask, data);
3098 if (err)
3099 return err;
3100 }
3101
3102 if (drv_type == DRV_TYPE_IO_SMIC) {
3103 ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
3104 data = BIT(bit + 16) | (((ret >> 2) & 0x1) << bit);
3105 err = regmap_write(regmap, reg, data);
3106 if (err)
3107 return err;
3108 }
3109
3110 return 0;
3111 }
3112
3113 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
3114 {
3115 PIN_CONFIG_BIAS_DISABLE,
3116 PIN_CONFIG_BIAS_PULL_UP,
3117 PIN_CONFIG_BIAS_PULL_DOWN,
3118 PIN_CONFIG_BIAS_BUS_HOLD
3119 },
3120 {
3121 PIN_CONFIG_BIAS_DISABLE,
3122 PIN_CONFIG_BIAS_PULL_DOWN,
3123 PIN_CONFIG_BIAS_DISABLE,
3124 PIN_CONFIG_BIAS_PULL_UP
3125 },
3126 };
3127
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)3128 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
3129 {
3130 struct rockchip_pinctrl *info = bank->drvdata;
3131 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3132 struct device *dev = info->dev;
3133 struct regmap *regmap;
3134 int reg, ret, pull_type;
3135 u8 bit;
3136 u32 data;
3137
3138 /* rk3066b does support any pulls */
3139 if (ctrl->type == RK3066B)
3140 return PIN_CONFIG_BIAS_DISABLE;
3141
3142 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3143 if (ret)
3144 return ret;
3145
3146 ret = regmap_read(regmap, reg, &data);
3147 if (ret)
3148 return ret;
3149
3150 switch (ctrl->type) {
3151 case RK2928:
3152 case RK3128:
3153 return !(data & BIT(bit))
3154 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
3155 : PIN_CONFIG_BIAS_DISABLE;
3156 case PX30:
3157 case RV1106:
3158 case RV1108:
3159 case RV1126:
3160 case RK1808:
3161 case RK3188:
3162 case RK3288:
3163 case RK3308:
3164 case RK3368:
3165 case RK3399:
3166 case RK3528:
3167 case RK3562:
3168 case RK3568:
3169 case RK3588:
3170 pull_type = bank->pull_type[pin_num / 8];
3171 data >>= bit;
3172 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
3173
3174 return rockchip_pull_list[pull_type][data];
3175 default:
3176 dev_err(dev, "unsupported pinctrl type\n");
3177 return -EINVAL;
3178 };
3179 }
3180
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)3181 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
3182 int pin_num, int pull)
3183 {
3184 struct rockchip_pinctrl *info = bank->drvdata;
3185 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3186 struct device *dev = info->dev;
3187 struct regmap *regmap;
3188 int reg, ret, i, pull_type;
3189 u8 bit;
3190 u32 data, rmask;
3191
3192 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
3193
3194 /* rk3066b does support any pulls */
3195 if (ctrl->type == RK3066B)
3196 return pull ? -EINVAL : 0;
3197
3198 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3199 if (ret)
3200 return ret;
3201
3202 switch (ctrl->type) {
3203 case RK2928:
3204 case RK3128:
3205 data = BIT(bit + 16);
3206 if (pull == PIN_CONFIG_BIAS_DISABLE)
3207 data |= BIT(bit);
3208 ret = regmap_write(regmap, reg, data);
3209 break;
3210 case PX30:
3211 case RV1106:
3212 case RV1108:
3213 case RV1126:
3214 case RK1808:
3215 case RK3188:
3216 case RK3288:
3217 case RK3308:
3218 case RK3368:
3219 case RK3399:
3220 case RK3528:
3221 case RK3562:
3222 case RK3568:
3223 case RK3588:
3224 pull_type = bank->pull_type[pin_num / 8];
3225 ret = -EINVAL;
3226 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
3227 i++) {
3228 if (rockchip_pull_list[pull_type][i] == pull) {
3229 ret = i;
3230 break;
3231 }
3232 }
3233 /*
3234 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3235 * where that pull up value becomes 3.
3236 */
3237 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
3238 if (ret == 1)
3239 ret = 3;
3240 }
3241
3242 if (ret < 0) {
3243 dev_err(dev, "unsupported pull setting %d\n", pull);
3244 return ret;
3245 }
3246
3247 /* enable the write to the equivalent lower bits */
3248 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
3249 rmask = data | (data >> 16);
3250 data |= (ret << bit);
3251
3252 ret = regmap_update_bits(regmap, reg, rmask, data);
3253 break;
3254 default:
3255 dev_err(dev, "unsupported pinctrl type\n");
3256 return -EINVAL;
3257 }
3258
3259 return ret;
3260 }
3261
3262 #define RK3328_SCHMITT_BITS_PER_PIN 1
3263 #define RK3328_SCHMITT_PINS_PER_REG 16
3264 #define RK3328_SCHMITT_BANK_STRIDE 8
3265 #define RK3328_SCHMITT_GRF_OFFSET 0x380
3266
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3267 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3268 int pin_num,
3269 struct regmap **regmap,
3270 int *reg, u8 *bit)
3271 {
3272 struct rockchip_pinctrl *info = bank->drvdata;
3273
3274 *regmap = info->regmap_base;
3275 *reg = RK3328_SCHMITT_GRF_OFFSET;
3276
3277 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
3278 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
3279 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
3280
3281 return 0;
3282 }
3283
3284 #define RK3568_SCHMITT_BITS_PER_PIN 2
3285 #define RK3568_SCHMITT_PINS_PER_REG 8
3286 #define RK3568_SCHMITT_BANK_STRIDE 0x10
3287 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
3288 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
3289
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3290 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3291 int pin_num,
3292 struct regmap **regmap,
3293 int *reg, u8 *bit)
3294 {
3295 struct rockchip_pinctrl *info = bank->drvdata;
3296
3297 if (bank->bank_num == 0) {
3298 *regmap = info->regmap_pmu;
3299 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
3300 } else {
3301 *regmap = info->regmap_base;
3302 *reg = RK3568_SCHMITT_GRF_OFFSET;
3303 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
3304 }
3305
3306 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
3307 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
3308 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
3309
3310 return 0;
3311 }
3312
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)3313 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
3314 {
3315 struct rockchip_pinctrl *info = bank->drvdata;
3316 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3317 struct regmap *regmap;
3318 int reg, ret;
3319 u8 bit;
3320 u32 data;
3321
3322 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3323 if (ret)
3324 return ret;
3325
3326 ret = regmap_read(regmap, reg, &data);
3327 if (ret)
3328 return ret;
3329
3330 data >>= bit;
3331 switch (ctrl->type) {
3332 case RK3562:
3333 case RK3568:
3334 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
3335 default:
3336 break;
3337 }
3338
3339 return data & 0x1;
3340 }
3341
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)3342 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
3343 int pin_num, int enable)
3344 {
3345 struct rockchip_pinctrl *info = bank->drvdata;
3346 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3347 struct device *dev = info->dev;
3348 struct regmap *regmap;
3349 int reg, ret;
3350 u8 bit;
3351 u32 data, rmask;
3352
3353 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
3354 bank->bank_num, pin_num, enable);
3355
3356 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3357 if (ret)
3358 return ret;
3359
3360 /* enable the write to the equivalent lower bits */
3361 switch (ctrl->type) {
3362 case RK3562:
3363 case RK3568:
3364 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
3365 rmask = data | (data >> 16);
3366 data |= ((enable ? 0x2 : 0x1) << bit);
3367 break;
3368 default:
3369 data = BIT(bit + 16) | (enable << bit);
3370 rmask = BIT(bit + 16) | BIT(bit);
3371 break;
3372 }
3373
3374 return regmap_update_bits(regmap, reg, rmask, data);
3375 }
3376
3377 #define PX30_SLEW_RATE_PMU_OFFSET 0x30
3378 #define PX30_SLEW_RATE_GRF_OFFSET 0x90
3379 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16
3380 #define PX30_SLEW_RATE_BANK_STRIDE 16
3381 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8
3382
px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3383 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
3384 int pin_num,
3385 struct regmap **regmap,
3386 int *reg, u8 *bit)
3387 {
3388 struct rockchip_pinctrl *info = bank->drvdata;
3389 int pins_per_reg;
3390
3391 if (bank->bank_num == 0) {
3392 *regmap = info->regmap_pmu;
3393 *reg = PX30_SLEW_RATE_PMU_OFFSET;
3394 pins_per_reg = PX30_SLEW_RATE_PINS_PER_PMU_REG;
3395 } else {
3396 *regmap = info->regmap_base;
3397 *reg = PX30_SLEW_RATE_GRF_OFFSET;
3398 pins_per_reg = PX30_SLEW_RATE_PINS_PER_GRF_REG;
3399 *reg += (bank->bank_num - 1) * PX30_SLEW_RATE_BANK_STRIDE;
3400 }
3401 *reg += ((pin_num / pins_per_reg) * 4);
3402 *bit = pin_num % pins_per_reg;
3403
3404 return 0;
3405 }
3406
rockchip_get_slew_rate(struct rockchip_pin_bank * bank,int pin_num)3407 static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num)
3408 {
3409 struct rockchip_pinctrl *info = bank->drvdata;
3410 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3411 struct regmap *regmap;
3412 int reg, ret;
3413 u8 bit;
3414 u32 data;
3415 int drv_type = bank->drv[pin_num / 8].drv_type;
3416
3417 if (drv_type == DRV_TYPE_IO_SMIC)
3418 return 0;
3419
3420 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
3421 if (ret)
3422 return ret;
3423
3424 ret = regmap_read(regmap, reg, &data);
3425 if (ret)
3426 return ret;
3427
3428 data >>= bit;
3429 return data & 0x1;
3430 }
3431
rockchip_set_slew_rate(struct rockchip_pin_bank * bank,int pin_num,int speed)3432 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank,
3433 int pin_num, int speed)
3434 {
3435 struct rockchip_pinctrl *info = bank->drvdata;
3436 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3437 struct regmap *regmap;
3438 int reg, ret;
3439 u8 bit;
3440 u32 data, rmask;
3441 int drv_type = bank->drv[pin_num / 8].drv_type;
3442
3443 if (drv_type == DRV_TYPE_IO_SMIC)
3444 return 0;
3445
3446 dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n",
3447 bank->bank_num, pin_num, speed);
3448
3449 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
3450 if (ret)
3451 return ret;
3452
3453 /* enable the write to the equivalent lower bits */
3454 data = BIT(bit + 16) | (speed << bit);
3455 rmask = BIT(bit + 16) | BIT(bit);
3456
3457 return regmap_update_bits(regmap, reg, rmask, data);
3458 }
3459
3460 /*
3461 * Pinmux_ops handling
3462 */
3463
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)3464 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3465 {
3466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3467
3468 return info->nfunctions;
3469 }
3470
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)3471 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
3472 unsigned selector)
3473 {
3474 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3475
3476 return info->functions[selector].name;
3477 }
3478
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)3479 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
3480 unsigned selector, const char * const **groups,
3481 unsigned * const num_groups)
3482 {
3483 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3484
3485 *groups = info->functions[selector].groups;
3486 *num_groups = info->functions[selector].ngroups;
3487
3488 return 0;
3489 }
3490
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)3491 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
3492 unsigned group)
3493 {
3494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3495 const unsigned int *pins = info->groups[group].pins;
3496 const struct rockchip_pin_config *data = info->groups[group].data;
3497 struct device *dev = info->dev;
3498 struct rockchip_pin_bank *bank;
3499 int cnt, ret = 0;
3500
3501 dev_dbg(dev, "enable function %s group %s\n",
3502 info->functions[selector].name, info->groups[group].name);
3503
3504 /*
3505 * for each pin in the pin group selected, program the corresponding
3506 * pin function number in the config register.
3507 */
3508 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
3509 bank = pin_to_bank(info, pins[cnt]);
3510 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
3511 data[cnt].func);
3512 if (ret)
3513 break;
3514 }
3515
3516 if (ret && cnt) {
3517 /* revert the already done pin settings */
3518 for (cnt--; cnt >= 0 && !data[cnt].func; cnt--)
3519 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
3520
3521 return ret;
3522 }
3523
3524 return 0;
3525 }
3526
3527 static const struct pinmux_ops rockchip_pmx_ops = {
3528 .get_functions_count = rockchip_pmx_get_funcs_count,
3529 .get_function_name = rockchip_pmx_get_func_name,
3530 .get_function_groups = rockchip_pmx_get_groups,
3531 .set_mux = rockchip_pmx_set,
3532 };
3533
3534 /*
3535 * Pinconf_ops handling
3536 */
3537
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)3538 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
3539 enum pin_config_param pull)
3540 {
3541 switch (ctrl->type) {
3542 case RK2928:
3543 case RK3128:
3544 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
3545 pull == PIN_CONFIG_BIAS_DISABLE);
3546 case RK3066B:
3547 return pull ? false : true;
3548 case PX30:
3549 case RV1106:
3550 case RV1108:
3551 case RV1126:
3552 case RK1808:
3553 case RK3188:
3554 case RK3288:
3555 case RK3308:
3556 case RK3368:
3557 case RK3399:
3558 case RK3528:
3559 case RK3562:
3560 case RK3568:
3561 case RK3588:
3562 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
3563 }
3564
3565 return false;
3566 }
3567
rockchip_pinconf_defer_pin(struct rockchip_pin_bank * bank,unsigned int pin,u32 param,u32 arg)3568 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
3569 unsigned int pin, u32 param, u32 arg)
3570 {
3571 struct rockchip_pin_deferred *cfg;
3572
3573 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
3574 if (!cfg)
3575 return -ENOMEM;
3576
3577 cfg->pin = pin;
3578 cfg->param = param;
3579 cfg->arg = arg;
3580
3581 list_add_tail(&cfg->head, &bank->deferred_pins);
3582
3583 return 0;
3584 }
3585
3586 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)3587 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3588 unsigned long *configs, unsigned num_configs)
3589 {
3590 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3591 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3592 struct gpio_chip *gpio = &bank->gpio_chip;
3593 enum pin_config_param param;
3594 u32 arg;
3595 int i;
3596 int rc;
3597
3598 for (i = 0; i < num_configs; i++) {
3599 param = pinconf_to_config_param(configs[i]);
3600 arg = pinconf_to_config_argument(configs[i]);
3601
3602 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
3603 /*
3604 * Check for gpio driver not being probed yet.
3605 * The lock makes sure that either gpio-probe has completed
3606 * or the gpio driver hasn't probed yet.
3607 */
3608 mutex_lock(&bank->deferred_lock);
3609 if (!gpio || !gpio->direction_output) {
3610 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
3611 arg);
3612 mutex_unlock(&bank->deferred_lock);
3613 if (rc)
3614 return rc;
3615
3616 break;
3617 }
3618 mutex_unlock(&bank->deferred_lock);
3619 }
3620
3621 switch (param) {
3622 case PIN_CONFIG_BIAS_DISABLE:
3623 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3624 param);
3625 if (rc)
3626 return rc;
3627 break;
3628 case PIN_CONFIG_BIAS_PULL_UP:
3629 case PIN_CONFIG_BIAS_PULL_DOWN:
3630 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3631 case PIN_CONFIG_BIAS_BUS_HOLD:
3632 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3633 return -ENOTSUPP;
3634
3635 if (!arg)
3636 return -EINVAL;
3637
3638 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3639 param);
3640 if (rc)
3641 return rc;
3642 break;
3643 case PIN_CONFIG_OUTPUT:
3644 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3645 RK_FUNC_GPIO);
3646 if (rc != RK_FUNC_GPIO)
3647 return -EINVAL;
3648
3649 rc = gpio->direction_output(gpio, pin - bank->pin_base,
3650 arg);
3651 if (rc)
3652 return rc;
3653 break;
3654 case PIN_CONFIG_INPUT_ENABLE:
3655 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3656 RK_FUNC_GPIO);
3657 if (rc != RK_FUNC_GPIO)
3658 return -EINVAL;
3659
3660 rc = gpio->direction_input(gpio, pin - bank->pin_base);
3661 if (rc)
3662 return rc;
3663 break;
3664 case PIN_CONFIG_DRIVE_STRENGTH:
3665 /* rk3288 is the first with per-pin drive-strength */
3666 if (!info->ctrl->drv_calc_reg)
3667 return -ENOTSUPP;
3668
3669 rc = rockchip_set_drive_perpin(bank,
3670 pin - bank->pin_base, arg);
3671 if (rc < 0)
3672 return rc;
3673 break;
3674 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3675 if (!info->ctrl->schmitt_calc_reg)
3676 return -ENOTSUPP;
3677
3678 rc = rockchip_set_schmitt(bank,
3679 pin - bank->pin_base, arg);
3680 if (rc < 0)
3681 return rc;
3682 break;
3683 case PIN_CONFIG_SLEW_RATE:
3684 if (!info->ctrl->slew_rate_calc_reg)
3685 return -ENOTSUPP;
3686
3687 rc = rockchip_set_slew_rate(bank,
3688 pin - bank->pin_base, arg);
3689 if (rc < 0)
3690 return rc;
3691 break;
3692 default:
3693 return -ENOTSUPP;
3694 }
3695 } /* for each config */
3696
3697 return 0;
3698 }
3699
3700 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)3701 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
3702 unsigned long *config)
3703 {
3704 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3705 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3706 struct gpio_chip *gpio = &bank->gpio_chip;
3707 enum pin_config_param param = pinconf_to_config_param(*config);
3708 u16 arg;
3709 int rc;
3710
3711 switch (param) {
3712 case PIN_CONFIG_BIAS_DISABLE:
3713 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3714 return -EINVAL;
3715
3716 arg = 0;
3717 break;
3718 case PIN_CONFIG_BIAS_PULL_UP:
3719 case PIN_CONFIG_BIAS_PULL_DOWN:
3720 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3721 case PIN_CONFIG_BIAS_BUS_HOLD:
3722 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3723 return -ENOTSUPP;
3724
3725 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3726 return -EINVAL;
3727
3728 arg = 1;
3729 break;
3730 case PIN_CONFIG_OUTPUT:
3731 rc = rockchip_get_mux(bank, pin - bank->pin_base);
3732 if (rc != RK_FUNC_GPIO)
3733 return -EINVAL;
3734
3735 if (!gpio || !gpio->get) {
3736 arg = 0;
3737 break;
3738 }
3739
3740 rc = gpio->get(gpio, pin - bank->pin_base);
3741 if (rc < 0)
3742 return rc;
3743
3744 arg = rc ? 1 : 0;
3745 break;
3746 case PIN_CONFIG_DRIVE_STRENGTH:
3747 /* rk3288 is the first with per-pin drive-strength */
3748 if (!info->ctrl->drv_calc_reg)
3749 return -ENOTSUPP;
3750
3751 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
3752 if (rc < 0)
3753 return rc;
3754
3755 arg = rc;
3756 break;
3757 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3758 if (!info->ctrl->schmitt_calc_reg)
3759 return -ENOTSUPP;
3760
3761 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
3762 if (rc < 0)
3763 return rc;
3764
3765 arg = rc;
3766 break;
3767 case PIN_CONFIG_SLEW_RATE:
3768 if (!info->ctrl->slew_rate_calc_reg)
3769 return -ENOTSUPP;
3770
3771 rc = rockchip_get_slew_rate(bank, pin - bank->pin_base);
3772 if (rc < 0)
3773 return rc;
3774
3775 arg = rc;
3776 break;
3777 default:
3778 return -ENOTSUPP;
3779 }
3780
3781 *config = pinconf_to_config_packed(param, arg);
3782
3783 return 0;
3784 }
3785
3786 static const struct pinconf_ops rockchip_pinconf_ops = {
3787 .pin_config_get = rockchip_pinconf_get,
3788 .pin_config_set = rockchip_pinconf_set,
3789 .is_generic = true,
3790 };
3791
3792 static const struct of_device_id rockchip_bank_match[] = {
3793 { .compatible = "rockchip,gpio-bank" },
3794 { .compatible = "rockchip,rk3188-gpio-bank0" },
3795 {},
3796 };
3797
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)3798 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3799 struct device_node *np)
3800 {
3801 struct device_node *child;
3802
3803 for_each_child_of_node(np, child) {
3804 if (of_match_node(rockchip_bank_match, child))
3805 continue;
3806
3807 info->nfunctions++;
3808 info->ngroups += of_get_child_count(child);
3809 }
3810 }
3811
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)3812 static int rockchip_pinctrl_parse_groups(struct device_node *np,
3813 struct rockchip_pin_group *grp,
3814 struct rockchip_pinctrl *info,
3815 u32 index)
3816 {
3817 struct device *dev = info->dev;
3818 struct rockchip_pin_bank *bank;
3819 int size;
3820 const __be32 *list;
3821 int num;
3822 int i, j;
3823 int ret;
3824
3825 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3826
3827 /* Initialise group */
3828 grp->name = np->name;
3829
3830 /*
3831 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3832 * do sanity check and calculate pins number
3833 */
3834 list = of_get_property(np, "rockchip,pins", &size);
3835 /* we do not check return since it's safe node passed down */
3836 size /= sizeof(*list);
3837 if (!size || size % 4)
3838 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3839
3840 grp->npins = size / 4;
3841
3842 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
3843 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3844 if (!grp->pins || !grp->data)
3845 return -ENOMEM;
3846
3847 for (i = 0, j = 0; i < size; i += 4, j++) {
3848 const __be32 *phandle;
3849 struct device_node *np_config;
3850
3851 num = be32_to_cpu(*list++);
3852 bank = bank_num_to_bank(info, num);
3853 if (IS_ERR(bank))
3854 return PTR_ERR(bank);
3855
3856 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3857 grp->data[j].func = be32_to_cpu(*list++);
3858
3859 phandle = list++;
3860 if (!phandle)
3861 return -EINVAL;
3862
3863 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
3864 ret = pinconf_generic_parse_dt_config(np_config, NULL,
3865 &grp->data[j].configs, &grp->data[j].nconfigs);
3866 if (ret)
3867 return ret;
3868 }
3869
3870 return 0;
3871 }
3872
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)3873 static int rockchip_pinctrl_parse_functions(struct device_node *np,
3874 struct rockchip_pinctrl *info,
3875 u32 index)
3876 {
3877 struct device *dev = info->dev;
3878 struct device_node *child;
3879 struct rockchip_pmx_func *func;
3880 struct rockchip_pin_group *grp;
3881 int ret;
3882 static u32 grp_index;
3883 u32 i = 0;
3884
3885 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3886
3887 func = &info->functions[index];
3888
3889 /* Initialise function */
3890 func->name = np->name;
3891 func->ngroups = of_get_child_count(np);
3892 if (func->ngroups <= 0)
3893 return 0;
3894
3895 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3896 if (!func->groups)
3897 return -ENOMEM;
3898
3899 for_each_child_of_node(np, child) {
3900 func->groups[i] = child->name;
3901 grp = &info->groups[grp_index++];
3902 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
3903 if (ret) {
3904 of_node_put(child);
3905 return ret;
3906 }
3907 }
3908
3909 return 0;
3910 }
3911
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)3912 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
3913 struct rockchip_pinctrl *info)
3914 {
3915 struct device *dev = &pdev->dev;
3916 struct device_node *np = dev->of_node;
3917 struct device_node *child;
3918 int ret;
3919 int i;
3920
3921 rockchip_pinctrl_child_count(info, np);
3922
3923 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3924 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3925
3926 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3927 if (!info->functions)
3928 return -ENOMEM;
3929
3930 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3931 if (!info->groups)
3932 return -ENOMEM;
3933
3934 i = 0;
3935
3936 for_each_child_of_node(np, child) {
3937 if (of_match_node(rockchip_bank_match, child))
3938 continue;
3939
3940 ret = rockchip_pinctrl_parse_functions(child, info, i++);
3941 if (ret) {
3942 dev_err(dev, "failed to parse function\n");
3943 of_node_put(child);
3944 return ret;
3945 }
3946 }
3947
3948 return 0;
3949 }
3950
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)3951 static int rockchip_pinctrl_register(struct platform_device *pdev,
3952 struct rockchip_pinctrl *info)
3953 {
3954 struct pinctrl_desc *ctrldesc = &info->pctl;
3955 struct pinctrl_pin_desc *pindesc, *pdesc;
3956 struct rockchip_pin_bank *pin_bank;
3957 struct device *dev = &pdev->dev;
3958 int pin, bank, ret;
3959 int k;
3960
3961 ctrldesc->name = "rockchip-pinctrl";
3962 ctrldesc->owner = THIS_MODULE;
3963 ctrldesc->pctlops = &rockchip_pctrl_ops;
3964 ctrldesc->pmxops = &rockchip_pmx_ops;
3965 ctrldesc->confops = &rockchip_pinconf_ops;
3966
3967 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3968 if (!pindesc)
3969 return -ENOMEM;
3970
3971 ctrldesc->pins = pindesc;
3972 ctrldesc->npins = info->ctrl->nr_pins;
3973
3974 pdesc = pindesc;
3975 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3976 pin_bank = &info->ctrl->pin_banks[bank];
3977 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3978 pdesc->number = k;
3979 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3980 pin_bank->name, pin);
3981 pdesc++;
3982 }
3983
3984 INIT_LIST_HEAD(&pin_bank->deferred_pins);
3985 mutex_init(&pin_bank->deferred_lock);
3986 }
3987
3988 ret = rockchip_pinctrl_parse_dt(pdev, info);
3989 if (ret)
3990 return ret;
3991
3992 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
3993 if (IS_ERR(info->pctl_dev))
3994 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3995
3996 return 0;
3997 }
3998
3999 static const struct of_device_id rockchip_pinctrl_dt_match[];
4000 static struct rockchip_pin_bank rk3308bs_pin_banks[];
4001 static struct rockchip_pin_bank px30s_pin_banks[];
4002
4003 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)4004 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
4005 struct rockchip_pinctrl *d,
4006 struct platform_device *pdev)
4007 {
4008 struct device *dev = &pdev->dev;
4009 struct device_node *node = dev->of_node;
4010 const struct of_device_id *match;
4011 struct rockchip_pin_ctrl *ctrl;
4012 struct rockchip_pin_bank *bank;
4013 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
4014
4015 match = of_match_node(rockchip_pinctrl_dt_match, node);
4016 ctrl = (struct rockchip_pin_ctrl *)match->data;
4017 if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
4018 ctrl->pin_banks = rk3308bs_pin_banks;
4019 if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
4020 ctrl->pin_banks = px30s_pin_banks;
4021
4022 grf_offs = ctrl->grf_mux_offset;
4023 pmu_offs = ctrl->pmu_mux_offset;
4024 drv_pmu_offs = ctrl->pmu_drv_offset;
4025 drv_grf_offs = ctrl->grf_drv_offset;
4026 bank = ctrl->pin_banks;
4027 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
4028 int bank_pins = 0;
4029
4030 raw_spin_lock_init(&bank->slock);
4031 bank->drvdata = d;
4032 bank->pin_base = ctrl->nr_pins;
4033 ctrl->nr_pins += bank->nr_pins;
4034
4035 /* calculate iomux and drv offsets */
4036 for (j = 0; j < 4; j++) {
4037 struct rockchip_iomux *iom = &bank->iomux[j];
4038 struct rockchip_drv *drv = &bank->drv[j];
4039 int inc;
4040
4041 if (bank_pins >= bank->nr_pins)
4042 break;
4043
4044 /* preset iomux offset value, set new start value */
4045 if (iom->offset >= 0) {
4046 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
4047 pmu_offs = iom->offset;
4048 else
4049 grf_offs = iom->offset;
4050 } else { /* set current iomux offset */
4051 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
4052 (iom->type & IOMUX_L_SOURCE_PMU)) ?
4053 pmu_offs : grf_offs;
4054 }
4055
4056 /* preset drv offset value, set new start value */
4057 if (drv->offset >= 0) {
4058 if (iom->type & IOMUX_SOURCE_PMU)
4059 drv_pmu_offs = drv->offset;
4060 else
4061 drv_grf_offs = drv->offset;
4062 } else { /* set current drv offset */
4063 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
4064 drv_pmu_offs : drv_grf_offs;
4065 }
4066
4067 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
4068 i, j, iom->offset, drv->offset);
4069
4070 /*
4071 * Increase offset according to iomux width.
4072 * 4bit iomux'es are spread over two registers.
4073 */
4074 inc = (iom->type & (IOMUX_WIDTH_4BIT |
4075 IOMUX_WIDTH_3BIT |
4076 IOMUX_WIDTH_2BIT)) ? 8 : 4;
4077 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
4078 pmu_offs += inc;
4079 else
4080 grf_offs += inc;
4081
4082 /*
4083 * Increase offset according to drv width.
4084 * 3bit drive-strenth'es are spread over two registers.
4085 */
4086 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
4087 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
4088 inc = 8;
4089 else
4090 inc = 4;
4091
4092 if (iom->type & IOMUX_SOURCE_PMU)
4093 drv_pmu_offs += inc;
4094 else
4095 drv_grf_offs += inc;
4096
4097 bank_pins += 8;
4098 }
4099
4100 /* calculate the per-bank recalced_mask */
4101 for (j = 0; j < ctrl->niomux_recalced; j++) {
4102 int pin = 0;
4103
4104 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
4105 pin = ctrl->iomux_recalced[j].pin;
4106 bank->recalced_mask |= BIT(pin);
4107 }
4108 }
4109
4110 /* calculate the per-bank route_mask */
4111 for (j = 0; j < ctrl->niomux_routes; j++) {
4112 int pin = 0;
4113
4114 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
4115 pin = ctrl->iomux_routes[j].pin;
4116 bank->route_mask |= BIT(pin);
4117 }
4118 }
4119 }
4120
4121 return ctrl;
4122 }
4123
4124 #define RK3288_GRF_GPIO6C_IOMUX 0x64
4125 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
4126
4127 static u32 rk3288_grf_gpio6c_iomux;
4128
rockchip_pinctrl_suspend(struct device * dev)4129 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
4130 {
4131 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4132 int ret = pinctrl_force_sleep(info->pctl_dev);
4133
4134 if (ret)
4135 return ret;
4136
4137 /*
4138 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
4139 * the setting here, and restore it at resume.
4140 */
4141 if (info->ctrl->type == RK3288) {
4142 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4143 &rk3288_grf_gpio6c_iomux);
4144 if (ret) {
4145 pinctrl_force_default(info->pctl_dev);
4146 return ret;
4147 }
4148 }
4149
4150 return 0;
4151 }
4152
rockchip_pinctrl_resume(struct device * dev)4153 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
4154 {
4155 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4156 int ret;
4157
4158 if (info->ctrl->type == RK3288) {
4159 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4160 rk3288_grf_gpio6c_iomux |
4161 GPIO6C6_SEL_WRITE_ENABLE);
4162 if (ret)
4163 return ret;
4164 }
4165
4166 return pinctrl_force_default(info->pctl_dev);
4167 }
4168
4169 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
4170 rockchip_pinctrl_resume);
4171
4172 /* SoC data specially handle */
4173
4174 /* rk3308 SoC data initialize */
4175 #define RK3308_GRF_SOC_CON13 0x608
4176 #define RK3308_GRF_SOC_CON15 0x610
4177
4178 /* RK3308_GRF_SOC_CON13 */
4179 #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
4180 #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
4181 #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
4182
4183 /* RK3308_GRF_SOC_CON15 */
4184 #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
4185 #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
4186 #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
4187
rk3308_soc_data_init(struct rockchip_pinctrl * info)4188 static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
4189 {
4190 int ret;
4191
4192 /*
4193 * Enable the special ctrl of selected sources.
4194 */
4195
4196 ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
4197 RK3308_GRF_I2C3_IOFUNC_SRC_CTRL |
4198 RK3308_GRF_GPIO2A3_SEL_SRC_CTRL |
4199 RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
4200 if (ret)
4201 return ret;
4202
4203 ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
4204 RK3308_GRF_GPIO2C0_SEL_SRC_CTRL |
4205 RK3308_GRF_GPIO3B3_SEL_SRC_CTRL |
4206 RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
4207
4208 return ret;
4209
4210 }
4211
rockchip_pinctrl_probe(struct platform_device * pdev)4212 static int rockchip_pinctrl_probe(struct platform_device *pdev)
4213 {
4214 struct rockchip_pinctrl *info;
4215 struct device *dev = &pdev->dev;
4216 struct device_node *np = dev->of_node, *node;
4217 struct rockchip_pin_ctrl *ctrl;
4218 struct resource *res;
4219 void __iomem *base;
4220 int ret;
4221
4222 if (!dev->of_node)
4223 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
4224
4225 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
4226 if (!info)
4227 return -ENOMEM;
4228
4229 info->dev = dev;
4230
4231 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
4232 if (!ctrl)
4233 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
4234 info->ctrl = ctrl;
4235
4236 node = of_parse_phandle(np, "rockchip,grf", 0);
4237 if (node) {
4238 info->regmap_base = syscon_node_to_regmap(node);
4239 of_node_put(node);
4240 if (IS_ERR(info->regmap_base))
4241 return PTR_ERR(info->regmap_base);
4242 } else {
4243 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
4244 if (IS_ERR(base))
4245 return PTR_ERR(base);
4246
4247 rockchip_regmap_config.max_register = resource_size(res) - 4;
4248 rockchip_regmap_config.name = "rockchip,pinctrl";
4249 info->regmap_base =
4250 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4251
4252 /* to check for the old dt-bindings */
4253 info->reg_size = resource_size(res);
4254
4255 /* Honor the old binding, with pull registers as 2nd resource */
4256 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
4257 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
4258 if (IS_ERR(base))
4259 return PTR_ERR(base);
4260
4261 rockchip_regmap_config.max_register = resource_size(res) - 4;
4262 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
4263 info->regmap_pull =
4264 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4265 }
4266 }
4267
4268 /* try to find the optional reference to the pmu syscon */
4269 node = of_parse_phandle(np, "rockchip,pmu", 0);
4270 if (node) {
4271 info->regmap_pmu = syscon_node_to_regmap(node);
4272 of_node_put(node);
4273 if (IS_ERR(info->regmap_pmu))
4274 return PTR_ERR(info->regmap_pmu);
4275 }
4276
4277 if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
4278 ret = rk3308_soc_data_init(info);
4279 if (ret)
4280 return ret;
4281 }
4282
4283 ret = rockchip_pinctrl_register(pdev, info);
4284 if (ret)
4285 return ret;
4286
4287 platform_set_drvdata(pdev, info);
4288 g_pctldev = info->pctl_dev;
4289
4290 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
4291 if (ret)
4292 return dev_err_probe(dev, ret, "failed to register gpio device\n");
4293
4294 dev_info(dev, "probed %s\n", dev_name(dev));
4295
4296 return 0;
4297 }
4298
rockchip_pinctrl_remove(struct platform_device * pdev)4299 static int rockchip_pinctrl_remove(struct platform_device *pdev)
4300 {
4301 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
4302 struct rockchip_pin_bank *bank;
4303 struct rockchip_pin_deferred *cfg;
4304 int i;
4305
4306 g_pctldev = NULL;
4307 of_platform_depopulate(&pdev->dev);
4308
4309 for (i = 0; i < info->ctrl->nr_banks; i++) {
4310 bank = &info->ctrl->pin_banks[i];
4311
4312 mutex_lock(&bank->deferred_lock);
4313 while (!list_empty(&bank->deferred_pins)) {
4314 cfg = list_first_entry(&bank->deferred_pins,
4315 struct rockchip_pin_deferred, head);
4316 list_del(&cfg->head);
4317 kfree(cfg);
4318 }
4319 mutex_unlock(&bank->deferred_lock);
4320 }
4321
4322 return 0;
4323 }
4324
4325 static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
4326 S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
4327 S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
4328 S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
4329 S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
4330 };
4331
4332 static struct rockchip_pin_bank px30_pin_banks[] = {
4333 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4334 IOMUX_SOURCE_PMU,
4335 IOMUX_SOURCE_PMU,
4336 IOMUX_SOURCE_PMU
4337 ),
4338 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4339 IOMUX_WIDTH_4BIT,
4340 IOMUX_WIDTH_4BIT,
4341 IOMUX_WIDTH_4BIT
4342 ),
4343 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4344 IOMUX_WIDTH_4BIT,
4345 IOMUX_WIDTH_4BIT,
4346 IOMUX_WIDTH_4BIT
4347 ),
4348 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4349 IOMUX_WIDTH_4BIT,
4350 IOMUX_WIDTH_4BIT,
4351 IOMUX_WIDTH_4BIT
4352 ),
4353 };
4354
4355 static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
4356 .pin_banks = px30_pin_banks,
4357 .nr_banks = ARRAY_SIZE(px30_pin_banks),
4358 .label = "PX30-GPIO",
4359 .type = PX30,
4360 .grf_mux_offset = 0x0,
4361 .pmu_mux_offset = 0x0,
4362 .iomux_routes = px30_mux_route_data,
4363 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
4364 .pull_calc_reg = px30_calc_pull_reg_and_bit,
4365 .drv_calc_reg = px30_calc_drv_reg_and_bit,
4366 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
4367 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
4368 };
4369
4370 static struct rockchip_pin_bank rv1106_pin_banks[] = {
4371 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
4372 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4373 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4374 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4375 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU),
4376 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4377 IOMUX_WIDTH_4BIT,
4378 IOMUX_WIDTH_4BIT,
4379 IOMUX_WIDTH_4BIT,
4380 IOMUX_WIDTH_4BIT,
4381 0, 0x08, 0x10, 0x18),
4382 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4383 IOMUX_WIDTH_4BIT,
4384 IOMUX_WIDTH_4BIT,
4385 IOMUX_WIDTH_4BIT,
4386 IOMUX_WIDTH_4BIT,
4387 0x10020, 0x10028, 0, 0),
4388 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4389 IOMUX_WIDTH_4BIT,
4390 IOMUX_WIDTH_4BIT,
4391 IOMUX_WIDTH_4BIT,
4392 IOMUX_WIDTH_4BIT,
4393 0x20040, 0x20048, 0x20050, 0x20058),
4394 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
4395 IOMUX_WIDTH_4BIT,
4396 IOMUX_WIDTH_4BIT,
4397 IOMUX_WIDTH_4BIT,
4398 0,
4399 0x30000, 0x30008, 0x30010, 0),
4400 };
4401
4402 static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
4403 .pin_banks = rv1106_pin_banks,
4404 .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
4405 .label = "RV1106-GPIO",
4406 .type = RV1106,
4407 .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
4408 .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
4409 .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
4410 };
4411
4412 static struct rockchip_pin_bank rv1108_pin_banks[] = {
4413 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4414 IOMUX_SOURCE_PMU,
4415 IOMUX_SOURCE_PMU,
4416 IOMUX_SOURCE_PMU),
4417 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4418 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
4419 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
4420 };
4421
4422 static struct rockchip_pin_ctrl rv1108_pin_ctrl __maybe_unused = {
4423 .pin_banks = rv1108_pin_banks,
4424 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
4425 .label = "RV1108-GPIO",
4426 .type = RV1108,
4427 .grf_mux_offset = 0x10,
4428 .pmu_mux_offset = 0x0,
4429 .iomux_recalced = rv1108_mux_recalced_data,
4430 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
4431 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
4432 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
4433 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
4434 };
4435
4436 static struct rockchip_pin_bank rv1126_pin_banks[] = {
4437 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
4438 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4439 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4440 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
4441 IOMUX_WIDTH_4BIT),
4442 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4443 IOMUX_WIDTH_4BIT,
4444 IOMUX_WIDTH_4BIT,
4445 IOMUX_WIDTH_4BIT,
4446 IOMUX_WIDTH_4BIT,
4447 0x10010, 0x10018, 0x10020, 0x10028),
4448 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
4449 IOMUX_WIDTH_4BIT,
4450 IOMUX_WIDTH_4BIT,
4451 IOMUX_WIDTH_4BIT,
4452 IOMUX_WIDTH_4BIT),
4453 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4454 IOMUX_WIDTH_4BIT,
4455 IOMUX_WIDTH_4BIT,
4456 IOMUX_WIDTH_4BIT,
4457 IOMUX_WIDTH_4BIT),
4458 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
4459 IOMUX_WIDTH_4BIT, 0, 0, 0),
4460 };
4461
4462 static struct rockchip_pin_ctrl rv1126_pin_ctrl __maybe_unused = {
4463 .pin_banks = rv1126_pin_banks,
4464 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
4465 .label = "RV1126-GPIO",
4466 .type = RV1126,
4467 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
4468 .pmu_mux_offset = 0x0,
4469 .iomux_routes = rv1126_mux_route_data,
4470 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
4471 .iomux_recalced = rv1126_mux_recalced_data,
4472 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
4473 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
4474 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
4475 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
4476 };
4477
4478 static struct rockchip_pin_bank rk1808_pin_banks[] = {
4479 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4480 IOMUX_SOURCE_PMU,
4481 IOMUX_SOURCE_PMU,
4482 IOMUX_SOURCE_PMU),
4483 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4484 IOMUX_WIDTH_4BIT,
4485 IOMUX_WIDTH_4BIT,
4486 IOMUX_WIDTH_4BIT),
4487 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4488 IOMUX_WIDTH_4BIT,
4489 IOMUX_WIDTH_4BIT,
4490 IOMUX_WIDTH_4BIT),
4491 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4492 IOMUX_WIDTH_4BIT,
4493 IOMUX_WIDTH_4BIT,
4494 IOMUX_WIDTH_4BIT),
4495 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4496 IOMUX_WIDTH_4BIT,
4497 IOMUX_WIDTH_4BIT,
4498 IOMUX_WIDTH_4BIT),
4499 };
4500
4501 static struct rockchip_pin_ctrl rk1808_pin_ctrl __maybe_unused = {
4502 .pin_banks = rk1808_pin_banks,
4503 .nr_banks = ARRAY_SIZE(rk1808_pin_banks),
4504 .label = "RK1808-GPIO",
4505 .type = RK1808,
4506 .iomux_routes = rk1808_mux_route_data,
4507 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
4508 .grf_mux_offset = 0x0,
4509 .pmu_mux_offset = 0x0,
4510 .pull_calc_reg = rk1808_calc_pull_reg_and_bit,
4511 .drv_calc_reg = rk1808_calc_drv_reg_and_bit,
4512 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
4513 .slew_rate_calc_reg = rk1808_calc_slew_rate_reg_and_bit,
4514 };
4515
4516 static struct rockchip_pin_bank rk2928_pin_banks[] = {
4517 PIN_BANK(0, 32, "gpio0"),
4518 PIN_BANK(1, 32, "gpio1"),
4519 PIN_BANK(2, 32, "gpio2"),
4520 PIN_BANK(3, 32, "gpio3"),
4521 };
4522
4523 static struct rockchip_pin_ctrl rk2928_pin_ctrl __maybe_unused = {
4524 .pin_banks = rk2928_pin_banks,
4525 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
4526 .label = "RK2928-GPIO",
4527 .type = RK2928,
4528 .grf_mux_offset = 0xa8,
4529 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4530 };
4531
4532 static struct rockchip_pin_bank rk3036_pin_banks[] = {
4533 PIN_BANK(0, 32, "gpio0"),
4534 PIN_BANK(1, 32, "gpio1"),
4535 PIN_BANK(2, 32, "gpio2"),
4536 };
4537
4538 static struct rockchip_pin_ctrl rk3036_pin_ctrl __maybe_unused = {
4539 .pin_banks = rk3036_pin_banks,
4540 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
4541 .label = "RK3036-GPIO",
4542 .type = RK2928,
4543 .grf_mux_offset = 0xa8,
4544 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4545 };
4546
4547 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
4548 PIN_BANK(0, 32, "gpio0"),
4549 PIN_BANK(1, 32, "gpio1"),
4550 PIN_BANK(2, 32, "gpio2"),
4551 PIN_BANK(3, 32, "gpio3"),
4552 PIN_BANK(4, 32, "gpio4"),
4553 PIN_BANK(6, 16, "gpio6"),
4554 };
4555
4556 static struct rockchip_pin_ctrl rk3066a_pin_ctrl __maybe_unused = {
4557 .pin_banks = rk3066a_pin_banks,
4558 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
4559 .label = "RK3066a-GPIO",
4560 .type = RK2928,
4561 .grf_mux_offset = 0xa8,
4562 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4563 };
4564
4565 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
4566 PIN_BANK(0, 32, "gpio0"),
4567 PIN_BANK(1, 32, "gpio1"),
4568 PIN_BANK(2, 32, "gpio2"),
4569 PIN_BANK(3, 32, "gpio3"),
4570 };
4571
4572 static struct rockchip_pin_ctrl rk3066b_pin_ctrl __maybe_unused = {
4573 .pin_banks = rk3066b_pin_banks,
4574 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
4575 .label = "RK3066b-GPIO",
4576 .type = RK3066B,
4577 .grf_mux_offset = 0x60,
4578 };
4579
4580 static struct rockchip_pin_bank rk3128_pin_banks[] = {
4581 PIN_BANK(0, 32, "gpio0"),
4582 PIN_BANK(1, 32, "gpio1"),
4583 PIN_BANK(2, 32, "gpio2"),
4584 PIN_BANK(3, 32, "gpio3"),
4585 };
4586
4587 static struct rockchip_pin_ctrl rk3128_pin_ctrl __maybe_unused = {
4588 .pin_banks = rk3128_pin_banks,
4589 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
4590 .label = "RK3128-GPIO",
4591 .type = RK3128,
4592 .grf_mux_offset = 0xa8,
4593 .iomux_recalced = rk3128_mux_recalced_data,
4594 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
4595 .iomux_routes = rk3128_mux_route_data,
4596 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
4597 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
4598 };
4599
4600 static struct rockchip_pin_bank rk3188_pin_banks[] = {
4601 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
4602 PIN_BANK(1, 32, "gpio1"),
4603 PIN_BANK(2, 32, "gpio2"),
4604 PIN_BANK(3, 32, "gpio3"),
4605 };
4606
4607 static struct rockchip_pin_ctrl rk3188_pin_ctrl __maybe_unused = {
4608 .pin_banks = rk3188_pin_banks,
4609 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
4610 .label = "RK3188-GPIO",
4611 .type = RK3188,
4612 .grf_mux_offset = 0x60,
4613 .iomux_routes = rk3188_mux_route_data,
4614 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
4615 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
4616 };
4617
4618 static struct rockchip_pin_bank rk3228_pin_banks[] = {
4619 PIN_BANK(0, 32, "gpio0"),
4620 PIN_BANK(1, 32, "gpio1"),
4621 PIN_BANK(2, 32, "gpio2"),
4622 PIN_BANK(3, 32, "gpio3"),
4623 };
4624
4625 static struct rockchip_pin_ctrl rk3228_pin_ctrl __maybe_unused = {
4626 .pin_banks = rk3228_pin_banks,
4627 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
4628 .label = "RK3228-GPIO",
4629 .type = RK3288,
4630 .grf_mux_offset = 0x0,
4631 .iomux_routes = rk3228_mux_route_data,
4632 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
4633 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4634 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4635 };
4636
4637 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4638 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
4639 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
4640 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
4641 IOMUX_UNROUTED
4642 ),
4643 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4644 IOMUX_UNROUTED,
4645 IOMUX_UNROUTED,
4646 0
4647 ),
4648 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4649 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4650 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4651 IOMUX_WIDTH_4BIT,
4652 0,
4653 0
4654 ),
4655 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4656 0,
4657 0,
4658 IOMUX_UNROUTED
4659 ),
4660 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4661 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4662 0,
4663 IOMUX_WIDTH_4BIT,
4664 IOMUX_UNROUTED
4665 ),
4666 PIN_BANK(8, 16, "gpio8"),
4667 };
4668
4669 static struct rockchip_pin_ctrl rk3288_pin_ctrl __maybe_unused = {
4670 .pin_banks = rk3288_pin_banks,
4671 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
4672 .label = "RK3288-GPIO",
4673 .type = RK3288,
4674 .grf_mux_offset = 0x0,
4675 .pmu_mux_offset = 0x84,
4676 .iomux_routes = rk3288_mux_route_data,
4677 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
4678 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
4679 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4680 };
4681
4682 static struct rockchip_pin_bank rk3308bs_pin_banks[] __maybe_unused = {
4683 S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
4684 S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
4685 S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
4686 S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
4687 S_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
4688 };
4689
4690 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4691 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4692 IOMUX_WIDTH_2BIT,
4693 IOMUX_WIDTH_2BIT,
4694 IOMUX_WIDTH_2BIT),
4695 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4696 IOMUX_WIDTH_2BIT,
4697 IOMUX_WIDTH_2BIT,
4698 IOMUX_WIDTH_2BIT),
4699 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4700 IOMUX_WIDTH_2BIT,
4701 IOMUX_WIDTH_2BIT,
4702 IOMUX_WIDTH_2BIT),
4703 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4704 IOMUX_WIDTH_2BIT,
4705 IOMUX_WIDTH_2BIT,
4706 IOMUX_WIDTH_2BIT),
4707 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4708 IOMUX_WIDTH_2BIT,
4709 IOMUX_WIDTH_2BIT,
4710 IOMUX_WIDTH_2BIT),
4711 };
4712
4713 static struct rockchip_pin_ctrl rk3308_pin_ctrl __maybe_unused = {
4714 .pin_banks = rk3308_pin_banks,
4715 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
4716 .label = "RK3308-GPIO",
4717 .type = RK3308,
4718 .grf_mux_offset = 0x0,
4719 .iomux_recalced = rk3308_mux_recalced_data,
4720 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4721 .iomux_routes = rk3308_mux_route_data,
4722 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4723 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4724 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4725 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
4726 .slew_rate_calc_reg = rk3308_calc_slew_rate_reg_and_bit,
4727 };
4728
4729 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4730 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4731 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4732 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4733 IOMUX_WIDTH_3BIT,
4734 IOMUX_WIDTH_3BIT,
4735 0),
4736 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4737 IOMUX_WIDTH_3BIT,
4738 IOMUX_WIDTH_3BIT,
4739 0,
4740 0),
4741 };
4742
4743 static struct rockchip_pin_ctrl rk3328_pin_ctrl __maybe_unused = {
4744 .pin_banks = rk3328_pin_banks,
4745 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4746 .label = "RK3328-GPIO",
4747 .type = RK3288,
4748 .grf_mux_offset = 0x0,
4749 .iomux_recalced = rk3328_mux_recalced_data,
4750 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4751 .iomux_routes = rk3328_mux_route_data,
4752 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4753 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4754 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4755 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4756 };
4757
4758 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4759 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4760 IOMUX_SOURCE_PMU,
4761 IOMUX_SOURCE_PMU,
4762 IOMUX_SOURCE_PMU
4763 ),
4764 PIN_BANK(1, 32, "gpio1"),
4765 PIN_BANK(2, 32, "gpio2"),
4766 PIN_BANK(3, 32, "gpio3"),
4767 };
4768
4769 static struct rockchip_pin_ctrl rk3368_pin_ctrl __maybe_unused = {
4770 .pin_banks = rk3368_pin_banks,
4771 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4772 .label = "RK3368-GPIO",
4773 .type = RK3368,
4774 .grf_mux_offset = 0x0,
4775 .pmu_mux_offset = 0x0,
4776 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4777 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4778 };
4779
4780 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4781 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4782 IOMUX_SOURCE_PMU,
4783 IOMUX_SOURCE_PMU,
4784 IOMUX_SOURCE_PMU,
4785 IOMUX_SOURCE_PMU,
4786 DRV_TYPE_IO_1V8_ONLY,
4787 DRV_TYPE_IO_1V8_ONLY,
4788 DRV_TYPE_IO_DEFAULT,
4789 DRV_TYPE_IO_DEFAULT,
4790 0x80,
4791 0x88,
4792 -1,
4793 -1,
4794 PULL_TYPE_IO_1V8_ONLY,
4795 PULL_TYPE_IO_1V8_ONLY,
4796 PULL_TYPE_IO_DEFAULT,
4797 PULL_TYPE_IO_DEFAULT
4798 ),
4799 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4800 IOMUX_SOURCE_PMU,
4801 IOMUX_SOURCE_PMU,
4802 IOMUX_SOURCE_PMU,
4803 DRV_TYPE_IO_1V8_OR_3V0,
4804 DRV_TYPE_IO_1V8_OR_3V0,
4805 DRV_TYPE_IO_1V8_OR_3V0,
4806 DRV_TYPE_IO_1V8_OR_3V0,
4807 0xa0,
4808 0xa8,
4809 0xb0,
4810 0xb8
4811 ),
4812 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4813 DRV_TYPE_IO_1V8_OR_3V0,
4814 DRV_TYPE_IO_1V8_ONLY,
4815 DRV_TYPE_IO_1V8_ONLY,
4816 PULL_TYPE_IO_DEFAULT,
4817 PULL_TYPE_IO_DEFAULT,
4818 PULL_TYPE_IO_1V8_ONLY,
4819 PULL_TYPE_IO_1V8_ONLY
4820 ),
4821 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4822 DRV_TYPE_IO_3V3_ONLY,
4823 DRV_TYPE_IO_3V3_ONLY,
4824 DRV_TYPE_IO_1V8_OR_3V0
4825 ),
4826 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4827 DRV_TYPE_IO_1V8_3V0_AUTO,
4828 DRV_TYPE_IO_1V8_OR_3V0,
4829 DRV_TYPE_IO_1V8_OR_3V0
4830 ),
4831 };
4832
4833 static struct rockchip_pin_ctrl rk3399_pin_ctrl __maybe_unused = {
4834 .pin_banks = rk3399_pin_banks,
4835 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
4836 .label = "RK3399-GPIO",
4837 .type = RK3399,
4838 .grf_mux_offset = 0xe000,
4839 .pmu_mux_offset = 0x0,
4840 .grf_drv_offset = 0xe100,
4841 .pmu_drv_offset = 0x80,
4842 .iomux_routes = rk3399_mux_route_data,
4843 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
4844 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
4845 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4846 };
4847
4848 static struct rockchip_pin_bank rk3528_pin_banks[] = {
4849 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4850 IOMUX_WIDTH_4BIT,
4851 IOMUX_WIDTH_4BIT,
4852 IOMUX_WIDTH_4BIT,
4853 IOMUX_WIDTH_4BIT,
4854 0, 0, 0, 0),
4855 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4856 IOMUX_WIDTH_4BIT,
4857 IOMUX_WIDTH_4BIT,
4858 IOMUX_WIDTH_4BIT,
4859 IOMUX_WIDTH_4BIT,
4860 0x20020, 0x20028, 0x20030, 0x20038),
4861 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4862 IOMUX_WIDTH_4BIT,
4863 IOMUX_WIDTH_4BIT,
4864 IOMUX_WIDTH_4BIT,
4865 IOMUX_WIDTH_4BIT,
4866 0x30040, 0, 0, 0),
4867 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4868 IOMUX_WIDTH_4BIT,
4869 IOMUX_WIDTH_4BIT,
4870 IOMUX_WIDTH_4BIT,
4871 IOMUX_WIDTH_4BIT,
4872 0x20060, 0x20068, 0x20070, 0),
4873 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
4874 IOMUX_WIDTH_4BIT,
4875 IOMUX_WIDTH_4BIT,
4876 IOMUX_WIDTH_4BIT,
4877 IOMUX_WIDTH_4BIT,
4878 0x10080, 0x10088, 0x10090, 0x10098),
4879 };
4880
4881 static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
4882 .pin_banks = rk3528_pin_banks,
4883 .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
4884 .label = "RK3528-GPIO",
4885 .type = RK3528,
4886 .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
4887 .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
4888 .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
4889 };
4890
4891 static struct rockchip_pin_bank rk3562_pin_banks[] = {
4892 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4893 IOMUX_WIDTH_4BIT,
4894 IOMUX_WIDTH_4BIT,
4895 IOMUX_WIDTH_4BIT,
4896 IOMUX_WIDTH_4BIT,
4897 0x20000, 0x20008, 0x20010, 0x20018),
4898 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4899 IOMUX_WIDTH_4BIT,
4900 IOMUX_WIDTH_4BIT,
4901 IOMUX_WIDTH_4BIT,
4902 IOMUX_WIDTH_4BIT,
4903 0, 0x08, 0x10, 0x18),
4904 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4905 IOMUX_WIDTH_4BIT,
4906 IOMUX_WIDTH_4BIT,
4907 IOMUX_WIDTH_4BIT,
4908 IOMUX_WIDTH_4BIT,
4909 0x20, 0, 0, 0),
4910 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4911 IOMUX_WIDTH_4BIT,
4912 IOMUX_WIDTH_4BIT,
4913 IOMUX_WIDTH_4BIT,
4914 IOMUX_WIDTH_4BIT,
4915 0x10040, 0x10048, 0x10050, 0x10058),
4916 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
4917 IOMUX_WIDTH_4BIT,
4918 IOMUX_WIDTH_4BIT,
4919 0,
4920 0,
4921 0x10060, 0x10068, 0, 0),
4922 };
4923
4924 static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
4925 .pin_banks = rk3562_pin_banks,
4926 .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
4927 .label = "RK3562-GPIO",
4928 .type = RK3562,
4929 .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
4930 .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
4931 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
4932 };
4933
4934 static struct rockchip_pin_bank rk3568_pin_banks[] = {
4935 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4936 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4937 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4938 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4939 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4940 IOMUX_WIDTH_4BIT,
4941 IOMUX_WIDTH_4BIT,
4942 IOMUX_WIDTH_4BIT),
4943 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4944 IOMUX_WIDTH_4BIT,
4945 IOMUX_WIDTH_4BIT,
4946 IOMUX_WIDTH_4BIT),
4947 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4948 IOMUX_WIDTH_4BIT,
4949 IOMUX_WIDTH_4BIT,
4950 IOMUX_WIDTH_4BIT),
4951 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4952 IOMUX_WIDTH_4BIT,
4953 IOMUX_WIDTH_4BIT,
4954 IOMUX_WIDTH_4BIT),
4955 };
4956
4957 static struct rockchip_pin_ctrl rk3568_pin_ctrl __maybe_unused = {
4958 .pin_banks = rk3568_pin_banks,
4959 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4960 .label = "RK3568-GPIO",
4961 .type = RK3568,
4962 .grf_mux_offset = 0x0,
4963 .pmu_mux_offset = 0x0,
4964 .grf_drv_offset = 0x0200,
4965 .pmu_drv_offset = 0x0070,
4966 .iomux_routes = rk3568_mux_route_data,
4967 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4968 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4969 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4970 .slew_rate_calc_reg = rk3568_calc_slew_rate_reg_and_bit,
4971 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4972 };
4973
4974 static struct rockchip_pin_bank rk3588_pin_banks[] = {
4975 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
4976 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4977 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
4978 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4979 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
4980 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4981 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
4982 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4983 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
4984 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4985 };
4986
4987 static struct rockchip_pin_ctrl rk3588_pin_ctrl __maybe_unused = {
4988 .pin_banks = rk3588_pin_banks,
4989 .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
4990 .label = "RK3588-GPIO",
4991 .type = RK3588,
4992 .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
4993 .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
4994 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
4995 };
4996
4997 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4998 #ifdef CONFIG_CPU_PX30
4999 { .compatible = "rockchip,px30-pinctrl",
5000 .data = &px30_pin_ctrl },
5001 #endif
5002 #ifdef CONFIG_CPU_RV1106
5003 { .compatible = "rockchip,rv1106-pinctrl",
5004 .data = &rv1106_pin_ctrl },
5005 #endif
5006 #ifdef CONFIG_CPU_RV1108
5007 { .compatible = "rockchip,rv1108-pinctrl",
5008 .data = &rv1108_pin_ctrl },
5009 #endif
5010 #ifdef CONFIG_CPU_RV1126
5011 { .compatible = "rockchip,rv1126-pinctrl",
5012 .data = &rv1126_pin_ctrl },
5013 #endif
5014 #ifdef CONFIG_CPU_RK1808
5015 { .compatible = "rockchip,rk1808-pinctrl",
5016 .data = &rk1808_pin_ctrl },
5017 #endif
5018 #ifdef CONFIG_CPU_RK2928
5019 { .compatible = "rockchip,rk2928-pinctrl",
5020 .data = &rk2928_pin_ctrl },
5021 #endif
5022 #ifdef CONFIG_CPU_RK3036
5023 { .compatible = "rockchip,rk3036-pinctrl",
5024 .data = &rk3036_pin_ctrl },
5025 #endif
5026 #ifdef CONFIG_CPU_RK30XX
5027 { .compatible = "rockchip,rk3066a-pinctrl",
5028 .data = &rk3066a_pin_ctrl },
5029 { .compatible = "rockchip,rk3066b-pinctrl",
5030 .data = &rk3066b_pin_ctrl },
5031 #endif
5032 #ifdef CONFIG_CPU_RK312X
5033 { .compatible = "rockchip,rk3128-pinctrl",
5034 .data = (void *)&rk3128_pin_ctrl },
5035 #endif
5036 #ifdef CONFIG_CPU_RK3188
5037 { .compatible = "rockchip,rk3188-pinctrl",
5038 .data = &rk3188_pin_ctrl },
5039 #endif
5040 #ifdef CONFIG_CPU_RK322X
5041 { .compatible = "rockchip,rk3228-pinctrl",
5042 .data = &rk3228_pin_ctrl },
5043 #endif
5044 #ifdef CONFIG_CPU_RK3288
5045 { .compatible = "rockchip,rk3288-pinctrl",
5046 .data = &rk3288_pin_ctrl },
5047 #endif
5048 #ifdef CONFIG_CPU_RK3308
5049 { .compatible = "rockchip,rk3308-pinctrl",
5050 .data = &rk3308_pin_ctrl },
5051 #endif
5052 #ifdef CONFIG_CPU_RK3328
5053 { .compatible = "rockchip,rk3328-pinctrl",
5054 .data = &rk3328_pin_ctrl },
5055 #endif
5056 #ifdef CONFIG_CPU_RK3368
5057 { .compatible = "rockchip,rk3368-pinctrl",
5058 .data = &rk3368_pin_ctrl },
5059 #endif
5060 #ifdef CONFIG_CPU_RK3399
5061 { .compatible = "rockchip,rk3399-pinctrl",
5062 .data = &rk3399_pin_ctrl },
5063 #endif
5064 #ifdef CONFIG_CPU_RK3528
5065 { .compatible = "rockchip,rk3528-pinctrl",
5066 .data = &rk3528_pin_ctrl },
5067 #endif
5068 #ifdef CONFIG_CPU_RK3562
5069 { .compatible = "rockchip,rk3562-pinctrl",
5070 .data = &rk3562_pin_ctrl },
5071 #endif
5072 #ifdef CONFIG_CPU_RK3568
5073 { .compatible = "rockchip,rk3568-pinctrl",
5074 .data = &rk3568_pin_ctrl },
5075 #endif
5076 #ifdef CONFIG_CPU_RK3588
5077 { .compatible = "rockchip,rk3588-pinctrl",
5078 .data = &rk3588_pin_ctrl },
5079 #endif
5080 {},
5081 };
5082
5083 static struct platform_driver rockchip_pinctrl_driver = {
5084 .probe = rockchip_pinctrl_probe,
5085 .remove = rockchip_pinctrl_remove,
5086 .driver = {
5087 .name = "rockchip-pinctrl",
5088 .pm = &rockchip_pinctrl_dev_pm_ops,
5089 .of_match_table = rockchip_pinctrl_dt_match,
5090 },
5091 };
5092
rockchip_pinctrl_drv_register(void)5093 static int __init rockchip_pinctrl_drv_register(void)
5094 {
5095 return platform_driver_register(&rockchip_pinctrl_driver);
5096 }
5097 postcore_initcall(rockchip_pinctrl_drv_register);
5098
rockchip_pinctrl_drv_unregister(void)5099 static void __exit rockchip_pinctrl_drv_unregister(void)
5100 {
5101 platform_driver_unregister(&rockchip_pinctrl_driver);
5102 }
5103 module_exit(rockchip_pinctrl_drv_unregister);
5104
5105 /**
5106 * rk_iomux_set - set the rockchip iomux by pin number.
5107 *
5108 * @bank: the gpio bank index, from 0 to the max bank num.
5109 * @pin: the gpio pin index, from 0 to 31.
5110 * @mux: the pointer to store mux value.
5111 *
5112 * Return 0 if set success, else return error code.
5113 */
rk_iomux_set(int bank,int pin,int mux)5114 int rk_iomux_set(int bank, int pin, int mux)
5115 {
5116 struct pinctrl_dev *pctldev = g_pctldev;
5117 struct rockchip_pinctrl *info;
5118 struct rockchip_pin_bank *gpio;
5119 struct rockchip_pin_group *grp = NULL;
5120 struct rockchip_pin_config *cfg = NULL;
5121 int i, j, ret;
5122
5123 if (!g_pctldev)
5124 return -ENODEV;
5125
5126 info = pinctrl_dev_get_drvdata(pctldev);
5127 if (bank >= info->ctrl->nr_banks)
5128 return -EINVAL;
5129
5130 if (pin > 31 || pin < 0)
5131 return -EINVAL;
5132
5133 gpio = &info->ctrl->pin_banks[bank];
5134
5135 mutex_lock(&iomux_lock);
5136 for (i = 0; i < info->ngroups; i++) {
5137 grp = &info->groups[i];
5138 for (j = 0; j < grp->npins; i++) {
5139 if (grp->pins[i] == (gpio->pin_base + pin)) {
5140 cfg = grp->data;
5141 break;
5142 }
5143 }
5144 }
5145
5146 ret = rockchip_set_mux(gpio, pin, mux);
5147 if (ret) {
5148 dev_err(info->dev, "mux GPIO%d-%d %d fail\n", bank, pin, mux);
5149 goto out;
5150 }
5151
5152 if (cfg && (cfg->func != mux))
5153 cfg->func = mux;
5154
5155 out:
5156 mutex_unlock(&iomux_lock);
5157
5158 return ret;
5159 }
5160 EXPORT_SYMBOL_GPL(rk_iomux_set);
5161
5162 /**
5163 * rk_iomux_get - get the rockchip iomux by pin number.
5164 *
5165 * @bank: the gpio bank index, from 0 to the max bank num.
5166 * @pin: the gpio pin index, from 0 to 31.
5167 * @mux: the pointer to store mux value.
5168 *
5169 * Return 0 if get success, else return error code.
5170 */
rk_iomux_get(int bank,int pin,int * mux)5171 int rk_iomux_get(int bank, int pin, int *mux)
5172 {
5173 struct pinctrl_dev *pctldev = g_pctldev;
5174 struct rockchip_pinctrl *info;
5175 struct rockchip_pin_bank *gpio;
5176 int ret;
5177
5178 if (!g_pctldev)
5179 return -ENODEV;
5180 if (!mux)
5181 return -EINVAL;
5182
5183 info = pinctrl_dev_get_drvdata(pctldev);
5184 if (bank >= info->ctrl->nr_banks)
5185 return -EINVAL;
5186
5187 if (pin > 31 || pin < 0)
5188 return -EINVAL;
5189
5190 gpio = &info->ctrl->pin_banks[bank];
5191
5192 mutex_lock(&iomux_lock);
5193 ret = rockchip_get_mux(gpio, pin);
5194 mutex_unlock(&iomux_lock);
5195
5196 *mux = ret;
5197
5198 return (ret >= 0) ? 0 : ret;
5199 }
5200 EXPORT_SYMBOL_GPL(rk_iomux_get);
5201
5202 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
5203 MODULE_LICENSE("GPL");
5204 MODULE_ALIAS("platform:pinctrl-rockchip");
5205 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
5206