1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 4 * Author: 5 * Finley Xiao <finley.xiao@rock-chips.com> 6 */ 7 8 #ifndef _ASM_ARCH_CRU_RK3506_H 9 #define _ASM_ARCH_CRU_RK3506_H 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define CPU_FREQ_HZ 589824000 16 17 /* RK3506 pll id */ 18 enum rk3506_pll_id { 19 GPLL, 20 V0PLL, 21 V1PLL, 22 PLL_COUNT, 23 }; 24 25 struct rk3506_clk_info { 26 unsigned long id; 27 char *name; 28 }; 29 30 struct rk3506_clk_priv { 31 struct rk3506_cru *cru; 32 ulong gpll_hz; 33 ulong gpll_div_hz; 34 ulong gpll_div_100mhz; 35 ulong v0pll_hz; 36 ulong v0pll_div_hz; 37 ulong v1pll_hz; 38 ulong v1pll_div_hz; 39 ulong armclk_hz; 40 ulong armclk_enter_hz; 41 ulong armclk_init_hz; 42 bool sync_kernel; 43 bool set_armclk_rate; 44 }; 45 46 struct rk3506_cru { 47 /* cru */ 48 uint32_t reserved0000[160]; /* offset 0x0 */ 49 uint32_t mode_con; /* offset 0x280 */ 50 uint32_t reserved0284[31]; /* offset 0x284 */ 51 uint32_t clksel_con[62]; /* offset 0x300 */ 52 uint32_t reserved03f8[258]; /* offset 0x3F8 */ 53 uint32_t gate_con[23]; /* offset 0x800 */ 54 uint32_t reserved085c[105]; /* offset 0x85C */ 55 uint32_t softrst_con[23]; /* offset 0xA00 */ 56 uint32_t reserved0a5c[105]; /* offset 0xA5C */ 57 uint32_t glb_cnt_th; /* offset 0xC00 */ 58 uint32_t glb_rst_st; /* offset 0xC04 */ 59 uint32_t glb_srst_fst; /* offset 0xC08 */ 60 uint32_t glb_srst_snd; /* offset 0xC0C */ 61 uint32_t glb_rst_con; /* offset 0xC10 */ 62 uint32_t reserved0c14[6]; /* offset 0xC14 */ 63 uint32_t corewfi_con; /* offset 0xC2C */ 64 uint32_t reserved0c30[15604]; /* offset 0xC30 */ 65 66 /* pmu cru */ 67 uint32_t gpll_con[5]; /* offset 0x10000 */ 68 uint32_t reserved10014[3]; /* offset 0x10014 */ 69 uint32_t v0pll_con[5]; /* offset 0x10020 */ 70 uint32_t reserved10034[3]; /* offset 0x10034 */ 71 uint32_t v1pll_con[5]; /* offset 0x10040 */ 72 uint32_t reserved10074[171]; /* offset 0x10054 */ 73 uint32_t pmuclksel_con[7]; /* offset 0x10300 */ 74 uint32_t reserved1031c[313]; /* offset 0x1031C */ 75 uint32_t pmugate_con[3]; /* offset 0x10800 */ 76 uint32_t reserved1080c[125]; /* offset 0x1080C */ 77 uint32_t pmusoftrst_con[2]; /* offset 0x10A00 */ 78 uint32_t reserved10a08[7583]; /* offset 0x10A08 */ 79 }; 80 81 check_member(rk3506_cru, reserved0c30[0], 0x0c30); 82 check_member(rk3506_cru, reserved10a08[0], 0x10a08); 83 84 struct pll_rate_table { 85 unsigned long rate; 86 unsigned int fbdiv; 87 unsigned int postdiv1; 88 unsigned int refdiv; 89 unsigned int postdiv2; 90 unsigned int dsmpd; 91 unsigned int frac; 92 }; 93 94 #define RK3506_PMU_CRU_BASE 0x10000 95 #define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE) 96 #define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 97 #define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 98 #define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 99 #define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE) 100 #define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE) 101 #define RK3506_MODE_CON 0x280 102 #define RK3506_GLB_CNT_TH 0xc00 103 #define RK3506_GLB_SRST_FST 0xc08 104 #define RK3506_GLB_SRST_SND 0xc0c 105 106 enum { 107 /* CRU_CLKSEL_CON00 */ 108 CLK_GPLL_DIV_SHIFT = 6, 109 CLK_GPLL_DIV_MASK = 0xf << CLK_GPLL_DIV_SHIFT, 110 CLK_GPLL_DIV_100M_SHIFT = 10, 111 CLK_GPLL_DIV_100M_MASK = 0xf << CLK_GPLL_DIV_100M_SHIFT, 112 113 /* CRU_CLKSEL_CON01 */ 114 CLK_V0PLL_DIV_SHIFT = 0, 115 CLK_V0PLL_DIV_MASK = 0xf << CLK_V0PLL_DIV_SHIFT, 116 CLK_V1PLL_DIV_SHIFT = 4, 117 CLK_V1PLL_DIV_MASK = 0xf << CLK_V1PLL_DIV_SHIFT, 118 119 /* CRU_CLKSEL_CON15 */ 120 CLK_CORE_SRC_DIV_SHIFT = 0, 121 CLK_CORE_SRC_DIV_MASK = 0x1f << CLK_CORE_SRC_DIV_SHIFT, 122 CLK_CORE_SRC_SEL_SHIFT = 5, 123 CLK_CORE_SRC_SEL_MASK = 0x3 << CLK_CORE_SRC_SEL_SHIFT, 124 CLK_CORE_SEL_GPLL = 0, 125 CLK_CORE_SEL_V0PLL, 126 CLK_CORE_SEL_V1PLL, 127 CLK_CORE_SRC_PVTMUX_SEL_SHIFT = 8, 128 CLK_CORE_SRC_PVTMUX_SEL_MASK = 0x1 << CLK_CORE_SRC_PVTMUX_SEL_SHIFT, 129 CLK_CORE_SRC_PRE = 0, 130 CLK_CORE_PVTPLL_SRC, 131 132 ACLK_CORE_DIV_SHIFT = 9, 133 ACLK_CORE_DIV_MASK = 0xf << ACLK_CORE_DIV_SHIFT, 134 135 /* CRU_CLKSEL_CON16 */ 136 PCLK_CORE_DIV_SHIFT = 0, 137 PCLK_CORE_DIV_MASK = 0xf << PCLK_CORE_DIV_SHIFT, 138 139 /* CRU_CLKSEL_CON21 */ 140 ACLK_BUS_DIV_SHIFT = 0, 141 ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 142 ACLK_BUS_SEL_SHIFT = 5, 143 ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 144 ACLK_BUS_SEL_GPLL_DIV = 0, 145 ACLK_BUS_SEL_V0PLL_DIV, 146 ACLK_BUS_SEL_V1PLL_DIV, 147 148 HCLK_BUS_DIV_SHIFT = 7, 149 HCLK_BUS_DIV_MASK = 0x1f << HCLK_BUS_DIV_SHIFT, 150 HCLK_BUS_SEL_SHIFT = 12, 151 HCLK_BUS_SEL_MASK = 0x3 << HCLK_BUS_SEL_SHIFT, 152 153 /* CRU_CLKSEL_CON22 */ 154 PCLK_BUS_DIV_SHIFT = 0, 155 PCLK_BUS_DIV_MASK = 0x1f << PCLK_BUS_DIV_SHIFT, 156 PCLK_BUS_SEL_SHIFT = 5, 157 PCLK_BUS_SEL_MASK = 0x3 << PCLK_BUS_SEL_SHIFT, 158 159 /* CRU_CLKSEL_CON29 */ 160 HCLK_LSPERI_DIV_SHIFT = 0, 161 HCLK_LSPERI_DIV_MASK = 0x1f << HCLK_LSPERI_DIV_SHIFT, 162 HCLK_LSPERI_SEL_SHIFT = 5, 163 HCLK_LSPERI_SEL_MASK = 0x3 << HCLK_LSPERI_SEL_SHIFT, 164 165 /* CRU_CLKSEL_CON32 */ 166 CLK_I2C0_DIV_SHIFT = 0, 167 CLK_I2C0_DIV_MASK = 0xf << CLK_I2C0_DIV_SHIFT, 168 CLK_I2C0_SEL_SHIFT = 4, 169 CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 170 CLK_I2C_SEL_GPLL = 0, 171 CLK_I2C_SEL_V0PLL, 172 CLK_I2C_SEL_V1PLL, 173 CLK_I2C1_DIV_SHIFT = 6, 174 CLK_I2C1_DIV_MASK = 0xf << CLK_I2C1_DIV_SHIFT, 175 CLK_I2C1_SEL_SHIFT = 10, 176 CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 177 178 /* CRU_CLKSEL_CON33 */ 179 CLK_I2C2_DIV_SHIFT = 0, 180 CLK_I2C2_DIV_MASK = 0xf << CLK_I2C2_DIV_SHIFT, 181 CLK_I2C2_SEL_SHIFT = 4, 182 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 183 CLK_PWM1_DIV_SHIFT = 6, 184 CLK_PWM1_DIV_MASK = 0xf << CLK_PWM1_DIV_SHIFT, 185 CLK_PWM1_SEL_SHIFT = 10, 186 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 187 CLK_PWM1_SEL_GPLL_DIV = 0, 188 CLK_PWM1_SEL_V0PLL_DIV, 189 CLK_PWM1_SEL_V1PLL_DIV, 190 191 /* CRU_CLKSEL_CON34 */ 192 CLK_SPI0_DIV_SHIFT = 4, 193 CLK_SPI0_DIV_MASK = 0xf << CLK_SPI0_DIV_SHIFT, 194 CLK_SPI0_SEL_SHIFT = 8, 195 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 196 CLK_SPI_SEL_24M = 0, 197 CLK_SPI_SEL_GPLL_DIV, 198 CLK_SPI_SEL_V0PLL_DIV, 199 CLK_SPI_SEL_V1PLL_DIV, 200 201 CLK_SPI1_DIV_SHIFT = 10, 202 CLK_SPI1_DIV_MASK = 0xf << CLK_SPI1_DIV_SHIFT, 203 CLK_SPI1_SEL_SHIFT = 14, 204 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 205 206 /* CRU_CLKSEL_CON49 */ 207 ACLK_HSPERI_DIV_SHIFT = 0, 208 ACLK_HSPERI_DIV_MASK = 0x1f << ACLK_HSPERI_DIV_SHIFT, 209 ACLK_HSPERI_SEL_SHIFT = 5, 210 ACLK_HSPERI_SEL_MASK = 0x3 << ACLK_HSPERI_SEL_SHIFT, 211 ACLK_HSPERI_SEL_GPLL_DIV = 0, 212 ACLK_HSPERI_SEL_V0PLL_DIV = 1, 213 ACLK_HSPERI_SEL_V1PLL_DIV = 2, 214 215 CCLK_SDMMC_DIV_SHIFT = 7, 216 CCLK_SDMMC_DIV_MASK = 0x3f << CCLK_SDMMC_DIV_SHIFT, 217 CCLK_SDMMC_SEL_SHIFT = 13, 218 CCLK_SDMMC_SEL_MASK = 0x3 << CCLK_SDMMC_SEL_SHIFT, 219 CCLK_SDMMC_SEL_24M = 0, 220 CCLK_SDMMC_SEL_GPLL, 221 CCLK_SDMMC_SEL_V0PLL, 222 CCLK_SDMMC_SEL_V1PLL, 223 224 /* CRU_CLKSEL_CON50 */ 225 SCLK_FSPI_DIV_SHIFT = 0, 226 SCLK_FSPI_DIV_MASK = 0x1f << SCLK_FSPI_DIV_SHIFT, 227 SCLK_FSPI_SEL_SHIFT = 5, 228 SCLK_FSPI_SEL_MASK = 0x3 << SCLK_FSPI_SEL_SHIFT, 229 SCLK_FSPI_SEL_24M = 0, 230 SCLK_FSPI_SEL_GPLL, 231 SCLK_FSPI_SEL_V0PLL, 232 SCLK_FSPI_SEL_V1PLL, 233 CLK_MAC_DIV_SHIFT = 7, 234 CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, 235 236 /* CRU_CLKSEL_CON54 */ 237 CLK_SARADC_DIV_SHIFT = 0, 238 CLK_SARADC_DIV_MASK = 0xf << CLK_SARADC_DIV_SHIFT, 239 CLK_SARADC_SEL_SHIFT = 4, 240 CLK_SARADC_SEL_MASK = 0x3 << CLK_SARADC_SEL_SHIFT, 241 CLK_SARADC_SEL_24M = 0, 242 CLK_SARADC_SEL_400K, 243 CLK_SARADC_SEL_32K, 244 245 /* CRU_CLKSEL_CON60 */ 246 DCLK_VOP_DIV_SHIFT = 0, 247 DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT, 248 DCLK_VOP_SEL_SHIFT = 8, 249 DCLK_VOP_SEL_MASK = 0x7 << DCLK_VOP_SEL_SHIFT, 250 DCLK_VOP_SEL_24M = 0, 251 DCLK_VOP_SEL_GPLL, 252 DCLK_VOP_SEL_V0PLL, 253 DCLK_VOP_SEL_V1PLL, 254 DCLK_VOP_SEL_FRAC_VOIC1, 255 DCLK_VOP_SEL_FRAC_COMMON0, 256 DCLK_VOP_SEL_FRAC_COMMON1, 257 DCLK_VOP_SEL_FRAC_COMMON2, 258 259 /* CRU_CLKSEL_CON61 */ 260 CLK_TSADC_DIV_SHIFT = 0, 261 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, 262 CLK_TSADC_TSEN_DIV_SHIFT = 8, 263 CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT, 264 265 /* PMUCRU_CLKSEL_CON00 */ 266 CLK_PWM0_DIV_SHIFT = 6, 267 CLK_PWM0_DIV_MASK = 0xf << CLK_PWM0_DIV_SHIFT, 268 CLK_MAC_OUT_DIV_SHIFT = 10, 269 CLK_MAC_OUT_DIV_MASK = 0x3f << CLK_MAC_OUT_DIV_SHIFT, 270 271 }; 272 #endif 273