1 /* 2 * (C) Copyright 2024 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_RK3506_H 7 #define _ASM_ARCH_GRF_RK3506_H 8 9 #include <common.h> 10 11 /* gpio0_ioc register structure define */ 12 struct rk3506_gpio0_ioc_reg { 13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */ 14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */ 15 uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */ 16 uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */ 17 uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */ 18 uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */ 19 uint32_t reserved0018[58]; /* address offset: 0x0018 */ 20 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */ 21 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */ 22 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */ 23 uint32_t gpio0a_ds_3; /* address offset: 0x010c */ 24 uint32_t gpio0b_ds_0; /* address offset: 0x0110 */ 25 uint32_t gpio0b_ds_1; /* address offset: 0x0114 */ 26 uint32_t gpio0b_ds_2; /* address offset: 0x0118 */ 27 uint32_t gpio0b_ds_3; /* address offset: 0x011c */ 28 uint32_t gpio0c_ds_0; /* address offset: 0x0120 */ 29 uint32_t gpio0c_ds_1; /* address offset: 0x0124 */ 30 uint32_t gpio0c_ds_2; /* address offset: 0x0128 */ 31 uint32_t gpio0c_ds_3; /* address offset: 0x012c */ 32 uint32_t reserved0130[52]; /* address offset: 0x0130 */ 33 uint32_t gpio0a_pull; /* address offset: 0x0200 */ 34 uint32_t gpio0b_pull; /* address offset: 0x0204 */ 35 uint32_t gpio0c_pull; /* address offset: 0x0208 */ 36 uint32_t reserved020c[61]; /* address offset: 0x020c */ 37 uint32_t gpio0a_ie; /* address offset: 0x0300 */ 38 uint32_t gpio0b_ie; /* address offset: 0x0304 */ 39 uint32_t gpio0c_ie; /* address offset: 0x0308 */ 40 uint32_t reserved030c[61]; /* address offset: 0x030c */ 41 uint32_t gpio0a_smt; /* address offset: 0x0400 */ 42 uint32_t gpio0b_smt; /* address offset: 0x0404 */ 43 uint32_t gpio0c_smt; /* address offset: 0x0408 */ 44 uint32_t reserved040c[61]; /* address offset: 0x040c */ 45 uint32_t gpio0a_sus; /* address offset: 0x0500 */ 46 uint32_t gpio0b_sus; /* address offset: 0x0504 */ 47 uint32_t gpio0c_sus; /* address offset: 0x0508 */ 48 uint32_t reserved050c[61]; /* address offset: 0x050c */ 49 uint32_t gpio0a_sl; /* address offset: 0x0600 */ 50 uint32_t gpio0b_sl; /* address offset: 0x0604 */ 51 uint32_t gpio0c_sl; /* address offset: 0x0608 */ 52 uint32_t reserved060c[61]; /* address offset: 0x060c */ 53 uint32_t gpio0a_od; /* address offset: 0x0700 */ 54 uint32_t gpio0b_od; /* address offset: 0x0704 */ 55 uint32_t gpio0c_od; /* address offset: 0x0708 */ 56 uint32_t reserved070c[61]; /* address offset: 0x070c */ 57 uint32_t gpio0_iddq; /* address offset: 0x0800 */ 58 uint32_t reserved0804[11]; /* address offset: 0x0804 */ 59 uint32_t gpio0d_con; /* address offset: 0x0830 */ 60 }; 61 62 check_member(rk3506_gpio0_ioc_reg, gpio0d_con, 0x0830); 63 64 /* gpio1_ioc register structure define */ 65 struct rk3506_gpio1_ioc_reg { 66 uint32_t reserved0000[8]; /* address offset: 0x0000 */ 67 uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */ 68 uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */ 69 uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */ 70 uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */ 71 uint32_t gpio1c_iomux_sel_0; /* address offset: 0x0030 */ 72 uint32_t gpio1c_iomux_sel_1; /* address offset: 0x0034 */ 73 uint32_t gpio1d_iomux_sel_0; /* address offset: 0x0038 */ 74 uint32_t reserved003c[65]; /* address offset: 0x003c */ 75 uint32_t gpio1a_ds_0; /* address offset: 0x0140 */ 76 uint32_t gpio1a_ds_1; /* address offset: 0x0144 */ 77 uint32_t gpio1a_ds_2; /* address offset: 0x0148 */ 78 uint32_t gpio1a_ds_3; /* address offset: 0x014c */ 79 uint32_t gpio1b_ds_0; /* address offset: 0x0150 */ 80 uint32_t gpio1b_ds_1; /* address offset: 0x0154 */ 81 uint32_t gpio1b_ds_2; /* address offset: 0x0158 */ 82 uint32_t gpio1b_ds_3; /* address offset: 0x015c */ 83 uint32_t gpio1c_ds_0; /* address offset: 0x0160 */ 84 uint32_t gpio1c_ds_1; /* address offset: 0x0164 */ 85 uint32_t gpio1c_ds_2; /* address offset: 0x0168 */ 86 uint32_t gpio1c_ds_3; /* address offset: 0x016c */ 87 uint32_t gpio1d_ds_0; /* address offset: 0x0170 */ 88 uint32_t gpio1d_ds_1; /* address offset: 0x0174 */ 89 uint32_t reserved0178[38]; /* address offset: 0x0178 */ 90 uint32_t gpio1a_pull; /* address offset: 0x0210 */ 91 uint32_t gpio1b_pull; /* address offset: 0x0214 */ 92 uint32_t gpio1c_pull; /* address offset: 0x0218 */ 93 uint32_t gpio1d_pull; /* address offset: 0x021c */ 94 uint32_t reserved0220[60]; /* address offset: 0x0220 */ 95 uint32_t gpio1a_ie; /* address offset: 0x0310 */ 96 uint32_t gpio1b_ie; /* address offset: 0x0314 */ 97 uint32_t gpio1c_ie; /* address offset: 0x0318 */ 98 uint32_t gpio1d_ie; /* address offset: 0x031c */ 99 uint32_t reserved0320[60]; /* address offset: 0x0320 */ 100 uint32_t gpio1a_smt; /* address offset: 0x0410 */ 101 uint32_t gpio1b_smt; /* address offset: 0x0414 */ 102 uint32_t gpio1c_smt; /* address offset: 0x0418 */ 103 uint32_t gpio1d_smt; /* address offset: 0x041c */ 104 uint32_t reserved0420[60]; /* address offset: 0x0420 */ 105 uint32_t gpio1a_sus; /* address offset: 0x0510 */ 106 uint32_t gpio1b_sus; /* address offset: 0x0514 */ 107 uint32_t gpio1c_sus; /* address offset: 0x0518 */ 108 uint32_t gpio1d_sus; /* address offset: 0x051c */ 109 uint32_t reserved0520[60]; /* address offset: 0x0520 */ 110 uint32_t gpio1a_sl; /* address offset: 0x0610 */ 111 uint32_t gpio1b_sl; /* address offset: 0x0614 */ 112 uint32_t gpio1c_sl; /* address offset: 0x0618 */ 113 uint32_t gpio1d_sl; /* address offset: 0x061c */ 114 uint32_t reserved0620[60]; /* address offset: 0x0620 */ 115 uint32_t gpio1a_od; /* address offset: 0x0710 */ 116 uint32_t gpio1b_od; /* address offset: 0x0714 */ 117 uint32_t gpio1c_od; /* address offset: 0x0718 */ 118 uint32_t gpio1d_od; /* address offset: 0x071c */ 119 uint32_t reserved0720[60]; /* address offset: 0x0720 */ 120 uint32_t gpio1_iddq; /* address offset: 0x0810 */ 121 }; 122 123 check_member(rk3506_gpio1_ioc_reg, gpio1_iddq, 0x0810); 124 125 /* gpio2_ioc register structure define */ 126 struct rk3506_gpio2_ioc_reg { 127 uint32_t reserved0000[16]; /* address offset: 0x0000 */ 128 uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */ 129 uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */ 130 uint32_t gpio2b_iomux_sel_0; /* address offset: 0x0048 */ 131 uint32_t gpio2b_iomux_sel_1; /* address offset: 0x004c */ 132 uint32_t gpio2c_iomux_sel_0; /* address offset: 0x0050 */ 133 uint32_t reserved0054[75]; /* address offset: 0x0054 */ 134 uint32_t gpio2a_ds_0; /* address offset: 0x0180 */ 135 uint32_t gpio2a_ds_1; /* address offset: 0x0184 */ 136 uint32_t gpio2a_ds_2; /* address offset: 0x0188 */ 137 uint32_t reserved018c; /* address offset: 0x018c */ 138 uint32_t gpio2b_ds_0; /* address offset: 0x0190 */ 139 uint32_t gpio2b_ds_1; /* address offset: 0x0194 */ 140 uint32_t gpio2b_ds_2; /* address offset: 0x0198 */ 141 uint32_t gpio2b_ds_3; /* address offset: 0x019c */ 142 uint32_t gpio2c_ds_0; /* address offset: 0x01a0 */ 143 uint32_t reserved01a4[31]; /* address offset: 0x01a4 */ 144 uint32_t gpio2a_pull; /* address offset: 0x0220 */ 145 uint32_t gpio2b_pull; /* address offset: 0x0224 */ 146 uint32_t gpio2c_pull; /* address offset: 0x0228 */ 147 uint32_t reserved022c[61]; /* address offset: 0x022c */ 148 uint32_t gpio2a_ie; /* address offset: 0x0320 */ 149 uint32_t gpio2b_ie; /* address offset: 0x0324 */ 150 uint32_t gpio2c_ie; /* address offset: 0x0328 */ 151 uint32_t reserved032c[61]; /* address offset: 0x032c */ 152 uint32_t gpio2a_smt; /* address offset: 0x0420 */ 153 uint32_t gpio2b_smt; /* address offset: 0x0424 */ 154 uint32_t gpio2c_smt; /* address offset: 0x0428 */ 155 uint32_t reserved042c[61]; /* address offset: 0x042c */ 156 uint32_t gpio2a_sus; /* address offset: 0x0520 */ 157 uint32_t gpio2b_sus; /* address offset: 0x0524 */ 158 uint32_t gpio2c_sus; /* address offset: 0x0528 */ 159 uint32_t reserved052c[61]; /* address offset: 0x052c */ 160 uint32_t gpio2a_sl; /* address offset: 0x0620 */ 161 uint32_t gpio2b_sl; /* address offset: 0x0624 */ 162 uint32_t gpio2c_sl; /* address offset: 0x0628 */ 163 uint32_t reserved062c[61]; /* address offset: 0x062c */ 164 uint32_t gpio2a_od; /* address offset: 0x0720 */ 165 uint32_t gpio2b_od; /* address offset: 0x0724 */ 166 uint32_t gpio2c_od; /* address offset: 0x0728 */ 167 uint32_t reserved072c[61]; /* address offset: 0x072c */ 168 uint32_t gpio2_iddq; /* address offset: 0x0820 */ 169 }; 170 171 check_member(rk3506_gpio2_ioc_reg, gpio2_iddq, 0x0820); 172 173 /* gpio3_ioc register structure define */ 174 struct rk3506_gpio3_ioc_reg { 175 uint32_t reserved0000[24]; /* address offset: 0x0000 */ 176 uint32_t gpio3a_iomux_sel_0; /* address offset: 0x0060 */ 177 uint32_t gpio3a_iomux_sel_1; /* address offset: 0x0064 */ 178 uint32_t gpio3b_iomux_sel_0; /* address offset: 0x0068 */ 179 uint32_t gpio3b_iomux_sel_1; /* address offset: 0x006c */ 180 uint32_t reserved0070[84]; /* address offset: 0x0070 */ 181 uint32_t gpio3a_ds_0; /* address offset: 0x01c0 */ 182 uint32_t gpio3a_ds_1; /* address offset: 0x01c4 */ 183 uint32_t gpio3a_ds_2; /* address offset: 0x01c8 */ 184 uint32_t gpio3a_ds_3; /* address offset: 0x01cc */ 185 uint32_t gpio3b_ds_0; /* address offset: 0x01d0 */ 186 uint32_t gpio3b_ds_1; /* address offset: 0x01d4 */ 187 uint32_t gpio3b_ds_2; /* address offset: 0x01d8 */ 188 uint32_t gpio3b_ds_3; /* address offset: 0x01dc */ 189 uint32_t reserved01e0[20]; /* address offset: 0x01e0 */ 190 uint32_t gpio3a_pull; /* address offset: 0x0230 */ 191 uint32_t gpio3b_pull; /* address offset: 0x0234 */ 192 uint32_t reserved0238[62]; /* address offset: 0x0238 */ 193 uint32_t gpio3a_ie; /* address offset: 0x0330 */ 194 uint32_t gpio3b_ie; /* address offset: 0x0334 */ 195 uint32_t reserved0338[62]; /* address offset: 0x0338 */ 196 uint32_t gpio3a_smt; /* address offset: 0x0430 */ 197 uint32_t gpio3b_smt; /* address offset: 0x0434 */ 198 uint32_t reserved0438[62]; /* address offset: 0x0438 */ 199 uint32_t gpio3a_sus; /* address offset: 0x0530 */ 200 uint32_t gpio3b_sus; /* address offset: 0x0534 */ 201 uint32_t reserved0538[62]; /* address offset: 0x0538 */ 202 uint32_t gpio3a_sl; /* address offset: 0x0630 */ 203 uint32_t gpio3b_sl; /* address offset: 0x0634 */ 204 uint32_t reserved0638[62]; /* address offset: 0x0638 */ 205 uint32_t gpio3a_od; /* address offset: 0x0730 */ 206 uint32_t gpio3b_od; /* address offset: 0x0734 */ 207 uint32_t reserved0738[58]; /* address offset: 0x0738 */ 208 uint32_t gpio3_iddq; /* address offset: 0x0820 */ 209 }; 210 211 check_member(rk3506_gpio3_ioc_reg, gpio3_iddq, 0x0820); 212 213 /* gpio4_ioc register structure define */ 214 struct rk3506_gpio4_ioc_reg { 215 uint32_t reserved0000[528]; /* address offset: 0x0000 */ 216 uint32_t saradc_con; /* address offset: 0x0840 */ 217 }; 218 219 check_member(rk3506_gpio4_ioc_reg, saradc_con, 0x0840); 220 221 #endif /* _ASM_ARCH_GRF_RK3506_H */ 222