1 /* 2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_IOC_RK3576_H 7 #define _ASM_ARCH_IOC_RK3576_H 8 9 #include <common.h> 10 11 /* pmu0_ioc register structure define */ 12 struct rk3576_pmu0_ioc_reg { 13 uint32_t gpio0a_iomux_sel_l; /* address offset: 0x0000 */ 14 uint32_t gpio0a_iomux_sel_h; /* address offset: 0x0004 */ 15 uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 16 uint32_t reserved000c; /* address offset: 0x000c */ 17 uint32_t gpio0a_ds_l; /* address offset: 0x0010 */ 18 uint32_t gpio0a_ds_h; /* address offset: 0x0014 */ 19 uint32_t gpio0b_ds_l; /* address offset: 0x0018 */ 20 uint32_t reserved001c; /* address offset: 0x001c */ 21 uint32_t gpio0a_pull; /* address offset: 0x0020 */ 22 uint32_t gpio0b_pull_l; /* address offset: 0x0024 */ 23 uint32_t gpio0a_ie; /* address offset: 0x0028 */ 24 uint32_t gpio0b_ie_l; /* address offset: 0x002c */ 25 uint32_t gpio0a_smt; /* address offset: 0x0030 */ 26 uint32_t gpio0b_smt_l; /* address offset: 0x0034 */ 27 uint32_t gpio0a_pdis; /* address offset: 0x0038 */ 28 uint32_t gpio0b_pdis_l; /* address offset: 0x003c */ 29 uint32_t osc_con; /* address offset: 0x0040 */ 30 }; 31 32 check_member(rk3576_pmu0_ioc_reg, osc_con, 0x0040); 33 34 /* pmu1_ioc register structure define */ 35 struct rk3576_pmu1_ioc_reg { 36 uint32_t gpio0b_iomux_sel_h; /* address offset: 0x0000 */ 37 uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0004 */ 38 uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0008 */ 39 uint32_t gpio0d_iomux_sel_l; /* address offset: 0x000c */ 40 uint32_t gpio0d_iomux_sel_h; /* address offset: 0x0010 */ 41 uint32_t gpio0b_ds_h; /* address offset: 0x0014 */ 42 uint32_t gpio0c_ds_l; /* address offset: 0x0018 */ 43 uint32_t gpio0c_ds_h; /* address offset: 0x001c */ 44 uint32_t gpio0d_ds_l; /* address offset: 0x0020 */ 45 uint32_t gpio0d_ds_h; /* address offset: 0x0024 */ 46 uint32_t gpio0b_pull_h; /* address offset: 0x0028 */ 47 uint32_t gpio0c_pull; /* address offset: 0x002c */ 48 uint32_t gpio0d_pull; /* address offset: 0x0030 */ 49 uint32_t gpio0b_ie_h; /* address offset: 0x0034 */ 50 uint32_t gpio0c_ie; /* address offset: 0x0038 */ 51 uint32_t gpio0d_ie; /* address offset: 0x003c */ 52 uint32_t gpio0b_smt_h; /* address offset: 0x0040 */ 53 uint32_t gpio0c_smt; /* address offset: 0x0044 */ 54 uint32_t gpio0d_smt; /* address offset: 0x0048 */ 55 uint32_t gpio0b_pdis_h; /* address offset: 0x004c */ 56 uint32_t gpio0c_pdis; /* address offset: 0x0050 */ 57 uint32_t gpio0d_pdis; /* address offset: 0x0054 */ 58 }; 59 60 check_member(rk3576_pmu1_ioc_reg, gpio0d_pdis, 0x0054); 61 62 /* top_ioc register structure define */ 63 struct rk3576_top_ioc_reg { 64 uint32_t reserved0000[2]; /* address offset: 0x0000 */ 65 uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 66 uint32_t gpio0b_iomux_sel_h; /* address offset: 0x000c */ 67 uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0010 */ 68 uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0014 */ 69 uint32_t gpio0d_iomux_sel_l; /* address offset: 0x0018 */ 70 uint32_t gpio0d_iomux_sel_h; /* address offset: 0x001c */ 71 uint32_t gpio1a_iomux_sel_l; /* address offset: 0x0020 */ 72 uint32_t gpio1a_iomux_sel_h; /* address offset: 0x0024 */ 73 uint32_t gpio1b_iomux_sel_l; /* address offset: 0x0028 */ 74 uint32_t gpio1b_iomux_sel_h; /* address offset: 0x002c */ 75 uint32_t gpio1c_iomux_sel_l; /* address offset: 0x0030 */ 76 uint32_t gpio1c_iomux_sel_h; /* address offset: 0x0034 */ 77 uint32_t gpio1d_iomux_sel_l; /* address offset: 0x0038 */ 78 uint32_t gpio1d_iomux_sel_h; /* address offset: 0x003c */ 79 uint32_t gpio2a_iomux_sel_l; /* address offset: 0x0040 */ 80 uint32_t gpio2a_iomux_sel_h; /* address offset: 0x0044 */ 81 uint32_t gpio2b_iomux_sel_l; /* address offset: 0x0048 */ 82 uint32_t gpio2b_iomux_sel_h; /* address offset: 0x004c */ 83 uint32_t gpio2c_iomux_sel_l; /* address offset: 0x0050 */ 84 uint32_t gpio2c_iomux_sel_h; /* address offset: 0x0054 */ 85 uint32_t gpio2d_iomux_sel_l; /* address offset: 0x0058 */ 86 uint32_t gpio2d_iomux_sel_h; /* address offset: 0x005c */ 87 uint32_t gpio3a_iomux_sel_l; /* address offset: 0x0060 */ 88 uint32_t gpio3a_iomux_sel_h; /* address offset: 0x0064 */ 89 uint32_t gpio3b_iomux_sel_l; /* address offset: 0x0068 */ 90 uint32_t gpio3b_iomux_sel_h; /* address offset: 0x006c */ 91 uint32_t gpio3c_iomux_sel_l; /* address offset: 0x0070 */ 92 uint32_t gpio3c_iomux_sel_h; /* address offset: 0x0074 */ 93 uint32_t gpio3d_iomux_sel_l; /* address offset: 0x0078 */ 94 uint32_t gpio3d_iomux_sel_h; /* address offset: 0x007c */ 95 uint32_t gpio4a_iomux_sel_l; /* address offset: 0x0080 */ 96 uint32_t gpio4a_iomux_sel_h; /* address offset: 0x0084 */ 97 uint32_t gpio4b_iomux_sel_l; /* address offset: 0x0088 */ 98 uint32_t gpio4b_iomux_sel_h; /* address offset: 0x008c */ 99 uint32_t reserved0090[24]; /* address offset: 0x0090 */ 100 uint32_t ioc_misc_con; /* address offset: 0x00f0 */ 101 uint32_t sdmmc_detn_flt; /* address offset: 0x00f4 */ 102 }; 103 104 check_member(rk3576_top_ioc_reg, sdmmc_detn_flt, 0x00f4); 105 106 /* vccio_ioc register structure define */ 107 struct rk3576_vccio_ioc_reg { 108 uint32_t reserved0000[8]; /* address offset: 0x0000 */ 109 uint32_t gpio1a_ds_l; /* address offset: 0x0020 */ 110 uint32_t gpio1a_ds_h; /* address offset: 0x0024 */ 111 uint32_t gpio1b_ds_l; /* address offset: 0x0028 */ 112 uint32_t gpio1b_ds_h; /* address offset: 0x002c */ 113 uint32_t gpio1c_ds_l; /* address offset: 0x0030 */ 114 uint32_t gpio1c_ds_h; /* address offset: 0x0034 */ 115 uint32_t gpio1d_ds_l; /* address offset: 0x0038 */ 116 uint32_t gpio1d_ds_h; /* address offset: 0x003c */ 117 uint32_t gpio2a_ds_l; /* address offset: 0x0040 */ 118 uint32_t gpio2a_ds_h; /* address offset: 0x0044 */ 119 uint32_t gpio2b_ds_l; /* address offset: 0x0048 */ 120 uint32_t gpio2b_ds_h; /* address offset: 0x004c */ 121 uint32_t gpio2c_ds_l; /* address offset: 0x0050 */ 122 uint32_t gpio2c_ds_h; /* address offset: 0x0054 */ 123 uint32_t gpio2d_ds_l; /* address offset: 0x0058 */ 124 uint32_t gpio2d_ds_h; /* address offset: 0x005c */ 125 uint32_t gpio3a_ds_l; /* address offset: 0x0060 */ 126 uint32_t gpio3a_ds_h; /* address offset: 0x0064 */ 127 uint32_t gpio3b_ds_l; /* address offset: 0x0068 */ 128 uint32_t gpio3b_ds_h; /* address offset: 0x006c */ 129 uint32_t gpio3c_ds_l; /* address offset: 0x0070 */ 130 uint32_t gpio3c_ds_h; /* address offset: 0x0074 */ 131 uint32_t gpio3d_ds_l; /* address offset: 0x0078 */ 132 uint32_t gpio3d_ds_h; /* address offset: 0x007c */ 133 uint32_t gpio4a_ds_l; /* address offset: 0x0080 */ 134 uint32_t gpio4a_ds_h; /* address offset: 0x0084 */ 135 uint32_t gpio4b_ds_l; /* address offset: 0x0088 */ 136 uint32_t gpio4b_ds_h; /* address offset: 0x008c */ 137 uint32_t reserved0090[32]; /* address offset: 0x0090 */ 138 uint32_t gpio1a_pull; /* address offset: 0x0110 */ 139 uint32_t gpio1b_pull; /* address offset: 0x0114 */ 140 uint32_t gpio1c_pull; /* address offset: 0x0118 */ 141 uint32_t gpio1d_pull; /* address offset: 0x011c */ 142 uint32_t gpio2a_pull; /* address offset: 0x0120 */ 143 uint32_t gpio2b_pull; /* address offset: 0x0124 */ 144 uint32_t gpio2c_pull; /* address offset: 0x0128 */ 145 uint32_t gpio2d_pull; /* address offset: 0x012c */ 146 uint32_t gpio3a_pull; /* address offset: 0x0130 */ 147 uint32_t gpio3b_pull; /* address offset: 0x0134 */ 148 uint32_t gpio3c_pull; /* address offset: 0x0138 */ 149 uint32_t gpio3d_pull; /* address offset: 0x013c */ 150 uint32_t gpio4a_pull; /* address offset: 0x0140 */ 151 uint32_t gpio4b_pull; /* address offset: 0x0144 */ 152 uint32_t reserved0148[14]; /* address offset: 0x0148 */ 153 uint32_t gpio1a_ie; /* address offset: 0x0180 */ 154 uint32_t gpio1b_ie; /* address offset: 0x0184 */ 155 uint32_t gpio1c_ie; /* address offset: 0x0188 */ 156 uint32_t gpio1d_ie; /* address offset: 0x018c */ 157 uint32_t gpio2a_ie; /* address offset: 0x0190 */ 158 uint32_t gpio2b_ie; /* address offset: 0x0194 */ 159 uint32_t gpio2c_ie; /* address offset: 0x0198 */ 160 uint32_t gpio2d_ie; /* address offset: 0x019c */ 161 uint32_t gpio3a_ie; /* address offset: 0x01a0 */ 162 uint32_t gpio3b_ie; /* address offset: 0x01a4 */ 163 uint32_t gpio3c_ie; /* address offset: 0x01a8 */ 164 uint32_t gpio3d_ie; /* address offset: 0x01ac */ 165 uint32_t gpio4a_ie; /* address offset: 0x01b0 */ 166 uint32_t gpio4b_ie; /* address offset: 0x01b4 */ 167 uint32_t reserved01b8[22]; /* address offset: 0x01b8 */ 168 uint32_t gpio1a_smt; /* address offset: 0x0210 */ 169 uint32_t gpio1b_smt; /* address offset: 0x0214 */ 170 uint32_t gpio1c_smt; /* address offset: 0x0218 */ 171 uint32_t gpio1d_smt; /* address offset: 0x021c */ 172 uint32_t gpio2a_smt; /* address offset: 0x0220 */ 173 uint32_t gpio2b_smt; /* address offset: 0x0224 */ 174 uint32_t gpio2c_smt; /* address offset: 0x0228 */ 175 uint32_t gpio2d_smt; /* address offset: 0x022c */ 176 uint32_t gpio3a_smt; /* address offset: 0x0230 */ 177 uint32_t gpio3b_smt; /* address offset: 0x0234 */ 178 uint32_t gpio3c_smt; /* address offset: 0x0238 */ 179 uint32_t gpio3d_smt; /* address offset: 0x023c */ 180 uint32_t gpio4a_smt; /* address offset: 0x0240 */ 181 uint32_t gpio4b_smt; /* address offset: 0x0244 */ 182 uint32_t reserved0248[14]; /* address offset: 0x0248 */ 183 uint32_t gpio1a_pdis; /* address offset: 0x0280 */ 184 uint32_t gpio1b_pdis; /* address offset: 0x0284 */ 185 uint32_t gpio1c_pdis; /* address offset: 0x0288 */ 186 uint32_t gpio1d_pdis; /* address offset: 0x028c */ 187 uint32_t gpio2a_pdis; /* address offset: 0x0290 */ 188 uint32_t gpio2b_pdis; /* address offset: 0x0294 */ 189 uint32_t gpio2c_pdis; /* address offset: 0x0298 */ 190 uint32_t gpio2d_pdis; /* address offset: 0x029c */ 191 uint32_t gpio3a_pdis; /* address offset: 0x02a0 */ 192 uint32_t gpio3b_pdis; /* address offset: 0x02a4 */ 193 uint32_t gpio3c_pdis; /* address offset: 0x02a8 */ 194 uint32_t gpio3d_pdis; /* address offset: 0x02ac */ 195 uint32_t gpio4a_pdis; /* address offset: 0x02b0 */ 196 uint32_t gpio4b_pdis; /* address offset: 0x02b4 */ 197 uint32_t reserved02b8[82]; /* address offset: 0x02b8 */ 198 uint32_t misc_con[9]; /* address offset: 0x0400 */ 199 }; 200 201 check_member(rk3576_vccio_ioc_reg, misc_con, 0x0400); 202 203 /* vccio6_ioc register structure define */ 204 struct rk3576_vccio6_ioc_reg { 205 uint32_t reserved0000[36]; /* address offset: 0x0000 */ 206 uint32_t gpio4c_ds_l; /* address offset: 0x0090 */ 207 uint32_t gpio4c_ds_h; /* address offset: 0x0094 */ 208 uint32_t reserved0098[44]; /* address offset: 0x0098 */ 209 uint32_t gpio4c_pull; /* address offset: 0x0148 */ 210 uint32_t reserved014c[27]; /* address offset: 0x014c */ 211 uint32_t gpio4c_ie; /* address offset: 0x01b8 */ 212 uint32_t reserved01bc[35]; /* address offset: 0x01bc */ 213 uint32_t gpio4c_smt; /* address offset: 0x0248 */ 214 uint32_t reserved024c[27]; /* address offset: 0x024c */ 215 uint32_t gpio4c_pdis; /* address offset: 0x02b8 */ 216 uint32_t reserved02bc[53]; /* address offset: 0x02bc */ 217 uint32_t gpio4c_iomux_sel_l; /* address offset: 0x0390 */ 218 uint32_t gpio4c_iomux_sel_h; /* address offset: 0x0394 */ 219 uint32_t reserved0398[26]; /* address offset: 0x0398 */ 220 uint32_t misc_con[2]; /* address offset: 0x0400 */ 221 uint32_t reserved0408[14]; /* address offset: 0x0408 */ 222 uint32_t hdmitx_hpd_status; /* address offset: 0x0440 */ 223 }; 224 225 check_member(rk3576_vccio6_ioc_reg, hdmitx_hpd_status, 0x0440); 226 227 /* vccio7_ioc register structure define */ 228 struct rk3576_vccio7_ioc_reg { 229 uint32_t reserved0000[38]; /* address offset: 0x0000 */ 230 uint32_t gpio4d_ds_l; /* address offset: 0x0098 */ 231 uint32_t reserved009c[44]; /* address offset: 0x009c */ 232 uint32_t gpio4d_pull; /* address offset: 0x014c */ 233 uint32_t reserved0150[27]; /* address offset: 0x0150 */ 234 uint32_t gpio4d_ie; /* address offset: 0x01bc */ 235 uint32_t reserved01c0[35]; /* address offset: 0x01c0 */ 236 uint32_t gpio4d_smt; /* address offset: 0x024c */ 237 uint32_t reserved0250[27]; /* address offset: 0x0250 */ 238 uint32_t gpio4d_pdis; /* address offset: 0x02bc */ 239 uint32_t reserved02c0[54]; /* address offset: 0x02c0 */ 240 uint32_t gpio4d_iomux_sel_l; /* address offset: 0x0398 */ 241 uint32_t reserved039c[25]; /* address offset: 0x039c */ 242 uint32_t xin_ufs_con; /* address offset: 0x0400 */ 243 }; 244 245 check_member(rk3576_vccio7_ioc_reg, xin_ufs_con, 0x0400); 246 247 #endif /* _ASM_ARCH_IOC_RK3576_H */ 248