1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * maxim-max96772.c -- I2C register interface access for max96772 serdes chip
4 *
5 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
6 *
7 * Author: luowei <lw@rock-chips.com>
8 */
9
10 #include "../core.h"
11 #include "maxim-max96772.h"
12
13 struct config_desc {
14 u16 reg;
15 u8 mask;
16 u8 val;
17 };
18
19 struct serdes_group_data {
20 const struct config_desc *configs;
21 int num_configs;
22 };
23
24 static int MAX96772_GPIO0_pins[] = {0};
25 static int MAX96772_GPIO1_pins[] = {1};
26 static int MAX96772_GPIO2_pins[] = {2};
27 static int MAX96772_GPIO3_pins[] = {3};
28 static int MAX96772_GPIO4_pins[] = {4};
29 static int MAX96772_GPIO5_pins[] = {5};
30 static int MAX96772_GPIO6_pins[] = {6};
31 static int MAX96772_GPIO7_pins[] = {7};
32
33 static int MAX96772_GPIO8_pins[] = {8};
34 static int MAX96772_GPIO9_pins[] = {9};
35 static int MAX96772_GPIO10_pins[] = {10};
36 static int MAX96772_GPIO11_pins[] = {11};
37 static int MAX96772_GPIO12_pins[] = {12};
38 static int MAX96772_GPIO13_pins[] = {13};
39 static int MAX96772_GPIO14_pins[] = {14};
40 static int MAX96772_GPIO15_pins[] = {15};
41
42 #define GROUP_DESC(nm) \
43 { \
44 .name = #nm, \
45 .pins = nm ## _pins, \
46 .num_pins = ARRAY_SIZE(nm ## _pins), \
47 }
48
49 struct serdes_function_data {
50 u8 gpio_out_dis:1;
51 u8 gpio_tx_en:1;
52 u8 gpio_rx_en:1;
53 u8 gpio_in_level:1;
54 u8 gpio_out_level:1;
55 u8 gpio_tx_id;
56 u8 gpio_rx_id;
57 u16 mdelay;
58 };
59
60 static const char *serdes_gpio_groups[] = {
61 "MAX96772_GPIO0", "MAX96772_GPIO1", "MAX96772_GPIO2", "MAX96772_GPIO3",
62 "MAX96772_GPIO4", "MAX96772_GPIO5", "MAX96772_GPIO6", "MAX96772_GPIO7",
63
64 "MAX96772_GPIO8", "MAX96772_GPIO9", "MAX96772_GPIO10", "MAX96772_GPIO11",
65 "MAX96772_GPIO12", "MAX96772_GPIO13", "MAX96772_GPIO14", "MAX96772_GPIO15",
66 };
67
68 #define FUNCTION_DESC_GPIO_INPUT_BYPASS(id) \
69 { \
70 .name = "SER_TO_DES_RXID"#id, \
71 .group_names = serdes_gpio_groups, \
72 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
73 .data = (void *)(const struct serdes_function_data []) { \
74 { .gpio_rx_en = 1, .gpio_rx_id = id } \
75 }, \
76 } \
77
78 #define FUNCTION_DESC_GPIO_OUTPUT_BYPASS(id) \
79 { \
80 .name = "DES_TXID"#id"_TO_SER", \
81 .group_names = serdes_gpio_groups, \
82 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
83 .data = (void *)(const struct serdes_function_data []) { \
84 { .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
85 }, \
86 } \
87
88 #define FUNCTION_DESC_GPIO_OUTPUT_LOW(id) \
89 { \
90 .name = "DES_TXID"#id"_OUTPUT_LOW", \
91 .group_names = serdes_gpio_groups, \
92 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
93 .data = (void *)(const struct serdes_function_data []) { \
94 { .gpio_out_dis = 0, .gpio_tx_en = 0, \
95 .gpio_rx_en = 0, .gpio_out_level = 0, .gpio_tx_id = id } \
96 }, \
97 } \
98
99 #define FUNCTION_DESC_GPIO_OUTPUT_HIGH(id) \
100 { \
101 .name = "DES_TXID"#id"_OUTPUT_HIGH", \
102 .group_names = serdes_gpio_groups, \
103 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
104 .data = (void *)(const struct serdes_function_data []) { \
105 { .gpio_out_dis = 0, .gpio_tx_en = 0, \
106 .gpio_rx_en = 0, .gpio_out_level = 1, .gpio_tx_id = id } \
107 }, \
108 } \
109
110 #define FUNCTION_DES_DELAY_MS(ms) \
111 { \
112 .name = "DELAY_"#ms"MS", \
113 .group_names = serdes_gpio_groups, \
114 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
115 .data = (void *)(const struct serdes_function_data []) { \
116 { .mdelay = ms, } \
117 }, \
118 } \
119
120 static struct pinctrl_pin_desc max96772_pins_desc[] = {
121 PINCTRL_PIN(MAXIM_MAX96772_GPIO0, "MAX96772_GPIO0"),
122 PINCTRL_PIN(MAXIM_MAX96772_GPIO1, "MAX96772_GPIO1"),
123 PINCTRL_PIN(MAXIM_MAX96772_GPIO2, "MAX96772_GPIO2"),
124 PINCTRL_PIN(MAXIM_MAX96772_GPIO3, "MAX96772_GPIO3"),
125 PINCTRL_PIN(MAXIM_MAX96772_GPIO4, "MAX96772_GPIO4"),
126 PINCTRL_PIN(MAXIM_MAX96772_GPIO5, "MAX96772_GPIO5"),
127 PINCTRL_PIN(MAXIM_MAX96772_GPIO6, "MAX96772_GPIO6"),
128 PINCTRL_PIN(MAXIM_MAX96772_GPIO7, "MAX96772_GPIO7"),
129
130 PINCTRL_PIN(MAXIM_MAX96772_GPIO8, "MAX96772_GPIO8"),
131 PINCTRL_PIN(MAXIM_MAX96772_GPIO9, "MAX96772_GPIO9"),
132 PINCTRL_PIN(MAXIM_MAX96772_GPIO10, "MAX96772_GPIO10"),
133 PINCTRL_PIN(MAXIM_MAX96772_GPIO11, "MAX96772_GPIO11"),
134 PINCTRL_PIN(MAXIM_MAX96772_GPIO12, "MAX96772_GPIO12"),
135 PINCTRL_PIN(MAXIM_MAX96772_GPIO13, "MAX96772_GPIO13"),
136 PINCTRL_PIN(MAXIM_MAX96772_GPIO14, "MAX96772_GPIO14"),
137 PINCTRL_PIN(MAXIM_MAX96772_GPIO15, "MAX96772_GPIO15"),
138 };
139
140 static struct group_desc max96772_groups_desc[] = {
141 GROUP_DESC(MAX96772_GPIO0),
142 GROUP_DESC(MAX96772_GPIO1),
143 GROUP_DESC(MAX96772_GPIO2),
144 GROUP_DESC(MAX96772_GPIO3),
145 GROUP_DESC(MAX96772_GPIO4),
146 GROUP_DESC(MAX96772_GPIO5),
147 GROUP_DESC(MAX96772_GPIO6),
148 GROUP_DESC(MAX96772_GPIO7),
149
150 GROUP_DESC(MAX96772_GPIO8),
151 GROUP_DESC(MAX96772_GPIO9),
152 GROUP_DESC(MAX96772_GPIO10),
153 GROUP_DESC(MAX96772_GPIO11),
154 GROUP_DESC(MAX96772_GPIO12),
155 GROUP_DESC(MAX96772_GPIO13),
156 GROUP_DESC(MAX96772_GPIO14),
157 GROUP_DESC(MAX96772_GPIO15),
158 };
159
160 static struct function_desc max96772_functions_desc[] = {
161 FUNCTION_DESC_GPIO_INPUT_BYPASS(0),
162 FUNCTION_DESC_GPIO_INPUT_BYPASS(1),
163 FUNCTION_DESC_GPIO_INPUT_BYPASS(2),
164 FUNCTION_DESC_GPIO_INPUT_BYPASS(3),
165 FUNCTION_DESC_GPIO_INPUT_BYPASS(4),
166 FUNCTION_DESC_GPIO_INPUT_BYPASS(5),
167 FUNCTION_DESC_GPIO_INPUT_BYPASS(6),
168 FUNCTION_DESC_GPIO_INPUT_BYPASS(7),
169
170 FUNCTION_DESC_GPIO_INPUT_BYPASS(8),
171 FUNCTION_DESC_GPIO_INPUT_BYPASS(9),
172 FUNCTION_DESC_GPIO_INPUT_BYPASS(10),
173 FUNCTION_DESC_GPIO_INPUT_BYPASS(11),
174 FUNCTION_DESC_GPIO_INPUT_BYPASS(12),
175 FUNCTION_DESC_GPIO_INPUT_BYPASS(13),
176 FUNCTION_DESC_GPIO_INPUT_BYPASS(14),
177 FUNCTION_DESC_GPIO_INPUT_BYPASS(15),
178
179 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(0),
180 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(1),
181 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(2),
182 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(3),
183 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(4),
184 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(5),
185 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(6),
186 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(7),
187
188 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(8),
189 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(9),
190 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(10),
191 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(11),
192 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(12),
193 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(13),
194 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(14),
195 FUNCTION_DESC_GPIO_OUTPUT_BYPASS(15),
196
197 FUNCTION_DESC_GPIO_OUTPUT_LOW(0),
198 FUNCTION_DESC_GPIO_OUTPUT_LOW(1),
199 FUNCTION_DESC_GPIO_OUTPUT_LOW(2),
200 FUNCTION_DESC_GPIO_OUTPUT_LOW(3),
201 FUNCTION_DESC_GPIO_OUTPUT_LOW(4),
202 FUNCTION_DESC_GPIO_OUTPUT_LOW(5),
203 FUNCTION_DESC_GPIO_OUTPUT_LOW(6),
204 FUNCTION_DESC_GPIO_OUTPUT_LOW(7),
205
206 FUNCTION_DESC_GPIO_OUTPUT_LOW(8),
207 FUNCTION_DESC_GPIO_OUTPUT_LOW(9),
208 FUNCTION_DESC_GPIO_OUTPUT_LOW(10),
209 FUNCTION_DESC_GPIO_OUTPUT_LOW(11),
210 FUNCTION_DESC_GPIO_OUTPUT_LOW(12),
211 FUNCTION_DESC_GPIO_OUTPUT_LOW(13),
212 FUNCTION_DESC_GPIO_OUTPUT_LOW(14),
213 FUNCTION_DESC_GPIO_OUTPUT_LOW(15),
214
215 FUNCTION_DESC_GPIO_OUTPUT_HIGH(0),
216 FUNCTION_DESC_GPIO_OUTPUT_HIGH(1),
217 FUNCTION_DESC_GPIO_OUTPUT_HIGH(2),
218 FUNCTION_DESC_GPIO_OUTPUT_HIGH(3),
219 FUNCTION_DESC_GPIO_OUTPUT_HIGH(4),
220 FUNCTION_DESC_GPIO_OUTPUT_HIGH(5),
221 FUNCTION_DESC_GPIO_OUTPUT_HIGH(6),
222 FUNCTION_DESC_GPIO_OUTPUT_HIGH(7),
223
224 FUNCTION_DESC_GPIO_OUTPUT_HIGH(8),
225 FUNCTION_DESC_GPIO_OUTPUT_HIGH(9),
226 FUNCTION_DESC_GPIO_OUTPUT_HIGH(10),
227 FUNCTION_DESC_GPIO_OUTPUT_HIGH(11),
228 FUNCTION_DESC_GPIO_OUTPUT_HIGH(12),
229 FUNCTION_DESC_GPIO_OUTPUT_HIGH(13),
230 FUNCTION_DESC_GPIO_OUTPUT_HIGH(14),
231 FUNCTION_DESC_GPIO_OUTPUT_HIGH(15),
232
233 FUNCTION_DES_DELAY_MS(10),
234 FUNCTION_DES_DELAY_MS(20),
235 FUNCTION_DES_DELAY_MS(30),
236 FUNCTION_DES_DELAY_MS(40),
237 FUNCTION_DES_DELAY_MS(50),
238 FUNCTION_DES_DELAY_MS(100),
239 FUNCTION_DES_DELAY_MS(200),
240 FUNCTION_DES_DELAY_MS(500),
241 };
242
243 static struct serdes_chip_pinctrl_info max96772_pinctrl_info = {
244 .pins = max96772_pins_desc,
245 .num_pins = ARRAY_SIZE(max96772_pins_desc),
246 .groups = max96772_groups_desc,
247 .num_groups = ARRAY_SIZE(max96772_groups_desc),
248 .functions = max96772_functions_desc,
249 .num_functions = ARRAY_SIZE(max96772_functions_desc),
250 };
251
252 static const struct reg_sequence max96772_clk_ref[3][14] = {
253 {
254 { 0xe7b2, 0x50 },
255 { 0xe7b3, 0x00 },
256 { 0xe7b4, 0xcc },
257 { 0xe7b5, 0x44 },
258 { 0xe7b6, 0x81 },
259 { 0xe7b7, 0x30 },
260 { 0xe7b8, 0x07 },
261 { 0xe7b9, 0x10 },
262 { 0xe7ba, 0x01 },
263 { 0xe7bb, 0x00 },
264 { 0xe7bc, 0x00 },
265 { 0xe7bd, 0x00 },
266 { 0xe7be, 0x52 },
267 { 0xe7bf, 0x00 },
268 }, {
269 { 0xe7b2, 0x50 },
270 { 0xe7b3, 0x00 },
271 { 0xe7b4, 0x00 },
272 { 0xe7b5, 0x40 },
273 { 0xe7b6, 0x6c },
274 { 0xe7b7, 0x20 },
275 { 0xe7b8, 0x07 },
276 { 0xe7b9, 0x00 },
277 { 0xe7ba, 0x01 },
278 { 0xe7bb, 0x00 },
279 { 0xe7bc, 0x00 },
280 { 0xe7bd, 0x00 },
281 { 0xe7be, 0x52 },
282 { 0xe7bf, 0x00 },
283 }, {
284 { 0xe7b2, 0x30 },
285 { 0xe7b3, 0x00 },
286 { 0xe7b4, 0x00 },
287 { 0xe7b5, 0x40 },
288 { 0xe7b6, 0x6c },
289 { 0xe7b7, 0x20 },
290 { 0xe7b8, 0x14 },
291 { 0xe7b9, 0x00 },
292 { 0xe7ba, 0x2e },
293 { 0xe7bb, 0x00 },
294 { 0xe7bc, 0x00 },
295 { 0xe7bd, 0x01 },
296 { 0xe7be, 0x32 },
297 { 0xe7bf, 0x00 },
298 }
299 };
300
max96772_aux_dpcd_read(struct serdes * serdes,unsigned int reg,unsigned int * value)301 static int max96772_aux_dpcd_read(struct serdes *serdes,
302 unsigned int reg,
303 unsigned int *value)
304 {
305 serdes_reg_write(serdes, 0xe778, reg & 0xff);
306 serdes_reg_write(serdes, 0xe779, (reg >> 8) & 0xff);
307 serdes_reg_write(serdes, 0xe77c, (reg >> 16) & 0xff);
308 serdes_reg_write(serdes, 0xe776, 0x10);
309 serdes_reg_write(serdes, 0xe777, 0x80);
310 /* FIXME */
311 mdelay(50);
312 serdes_reg_read(serdes, 0xe77a, value);
313
314 return 0;
315 }
316
max96772_panel_init(struct serdes * serdes)317 static int max96772_panel_init(struct serdes *serdes)
318 {
319 return 0;
320 }
321
max96772_panel_prepare(struct serdes * serdes)322 static int max96772_panel_prepare(struct serdes *serdes)
323 {
324 const struct drm_display_mode *mode = &serdes->serdes_panel->mode;
325 u32 hfp, hsa, hbp, hact;
326 u32 vact, vsa, vfp, vbp;
327 u64 hwords, mvid;
328 bool hsync_pol, vsync_pol;
329
330 serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate);
331 serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count);
332
333 if (serdes->serdes_panel->ssc) {
334 serdes_reg_write(serdes, 0xe7b0, 0x01);
335 serdes_reg_write(serdes, 0xe7b1, 0x10);
336 } else {
337 serdes_reg_write(serdes, 0xe7b1, 0x00);
338 }
339
340 switch (serdes->serdes_panel->link_rate) {
341 case DP_LINK_BW_5_4:
342 serdes_multi_reg_write(serdes, max96772_clk_ref[2],
343 ARRAY_SIZE(max96772_clk_ref[2]));
344 break;
345 case DP_LINK_BW_2_7:
346 serdes_multi_reg_write(serdes, max96772_clk_ref[1],
347 ARRAY_SIZE(max96772_clk_ref[1]));
348 break;
349 case DP_LINK_BW_1_62:
350 default:
351 serdes_multi_reg_write(serdes, max96772_clk_ref[0],
352 ARRAY_SIZE(max96772_clk_ref[0]));
353 break;
354 }
355
356 vact = mode->vdisplay;
357 vsa = mode->vsync_end - mode->vsync_start;
358 vfp = mode->vsync_start - mode->vdisplay;
359 vbp = mode->vtotal - mode->vsync_end;
360 hact = mode->hdisplay;
361 hsa = mode->hsync_end - mode->hsync_start;
362 hfp = mode->hsync_start - mode->hdisplay;
363 hbp = mode->htotal - mode->hsync_end;
364
365 serdes_reg_write(serdes, 0xe794, hact & 0xff);
366 serdes_reg_write(serdes, 0xe795, (hact >> 8) & 0xff);
367 serdes_reg_write(serdes, 0xe796, hfp & 0xff);
368 serdes_reg_write(serdes, 0xe797, (hfp >> 8) & 0xff);
369 serdes_reg_write(serdes, 0xe798, hsa & 0xff);
370 serdes_reg_write(serdes, 0xe799, (hsa >> 8) & 0xff);
371 serdes_reg_write(serdes, 0xe79a, hbp & 0xff);
372 serdes_reg_write(serdes, 0xe79b, (hbp >> 8) & 0xff);
373 serdes_reg_write(serdes, 0xe79c, vact & 0xff);
374 serdes_reg_write(serdes, 0xe79d, (vact >> 8) & 0xff);
375 serdes_reg_write(serdes, 0xe79e, vfp & 0xff);
376 serdes_reg_write(serdes, 0xe79f, (vfp >> 8) & 0xff);
377 serdes_reg_write(serdes, 0xe7a0, vsa & 0xff);
378 serdes_reg_write(serdes, 0xe7a1, (vsa >> 8) & 0xff);
379 serdes_reg_write(serdes, 0xe7a2, vbp & 0xff);
380 serdes_reg_write(serdes, 0xe7a3, (vbp >> 8) & 0xff);
381
382 hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
383 vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
384 serdes_reg_write(serdes, 0xe7ac, hsync_pol | (vsync_pol << 1));
385
386 /* NVID should always be set to 0x8000 */
387 serdes_reg_write(serdes, 0xe7a8, 0);
388 serdes_reg_write(serdes, 0xe7a9, 0x80);
389
390 /* HWORDS = ((HRES x bits / pixel) / 16) - LANE_COUNT */
391 hwords = DIV_ROUND_UP(hact * 24, 16) - serdes->serdes_panel->lane_count;
392 serdes_reg_write(serdes, 0xe7a4, hwords);
393 serdes_reg_write(serdes, 0xe7a5, hwords >> 8);
394
395 /* MVID = (PCLK x NVID) x 10 / Link Rate */
396 mvid = DIV_ROUND_UP((u64)mode->clock * 32768,
397 drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate));
398 serdes_reg_write(serdes, 0xe7a6, mvid & 0xff);
399 serdes_reg_write(serdes, 0xe7a7, (mvid >> 8) & 0xff);
400
401 serdes_reg_write(serdes, 0xe7aa, 0x40);
402 serdes_reg_write(serdes, 0xe7ab, 0x00);
403
404 return 0;
405 }
406
max96772_panel_unprepare(struct serdes * serdes)407 static int max96772_panel_unprepare(struct serdes *serdes)
408 {
409 return 0;
410 }
411
max96772_panel_enable(struct serdes * serdes)412 static int max96772_panel_enable(struct serdes *serdes)
413 {
414 u32 status[2];
415 u32 val;
416 int ret;
417 int i = 0;
418
419 /* Run link training */
420 serdes_reg_write(serdes, 0xe776, 0x02);
421 serdes_reg_write(serdes, 0xe777, 0x80);
422
423 for (i = 0; i < 100; i++) {
424 ret = serdes_reg_read(serdes, 0x07f0, &val);
425 if (val & 0x01)
426 break;
427 mdelay(5);
428 }
429
430 ret = max96772_aux_dpcd_read(serdes, DP_LANE0_1_STATUS, &status[0]);
431 if (ret)
432 return ret;
433
434 ret = max96772_aux_dpcd_read(serdes, DP_LANE2_3_STATUS, &status[1]);
435 if (ret)
436 return ret;
437
438 dev_err(serdes->dev, "Link Training failed: LANE0_1_STATUS=0x%02x, LANE2_3_STATUS=0x%02x\n",
439 status[0], status[1]);
440
441 return 0;
442 }
443
max96772_panel_disable(struct serdes * serdes)444 static int max96772_panel_disable(struct serdes *serdes)
445 {
446 return 0;
447 }
448
max96772_panel_backlight_enable(struct serdes * serdes)449 int max96772_panel_backlight_enable(struct serdes *serdes)
450 {
451 return 0;
452 }
453
max96772_panel_backlight_disable(struct serdes * serdes)454 int max96772_panel_backlight_disable(struct serdes *serdes)
455 {
456 return 0;
457 }
458
459 static struct serdes_chip_panel_ops max96772_panel_ops = {
460 .init = max96772_panel_init,
461 .prepare = max96772_panel_prepare,
462 .unprepare = max96772_panel_unprepare,
463 .enable = max96772_panel_enable,
464 .disable = max96772_panel_disable,
465 .backlight_enable = max96772_panel_backlight_enable,
466 .backlight_disable = max96772_panel_backlight_disable,
467 };
468
max96772_pinctrl_set_pin_mux(struct serdes * serdes,unsigned int pin_selector,unsigned int func_selector)469 static int max96772_pinctrl_set_pin_mux(struct serdes *serdes,
470 unsigned int pin_selector,
471 unsigned int func_selector)
472 {
473 struct function_desc *func;
474 struct pinctrl_pin_desc *pin;
475 int offset;
476 u16 ms;
477
478 func = &serdes->chip_data->pinctrl_info->functions[func_selector];
479 if (!func) {
480 printf("%s: func is null\n", __func__);
481 return -EINVAL;
482 }
483
484 pin = &serdes->chip_data->pinctrl_info->pins[pin_selector];
485 if (!pin) {
486 printf("%s: pin is null\n", __func__);
487 return -EINVAL;
488 }
489
490 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p pin=%s num=%d\n",
491 __func__, serdes->dev->name,
492 func->name, func->data,
493 pin->name, pin->number);
494
495 if (func->data) {
496 struct serdes_function_data *fdata = func->data;
497
498 ms = fdata->mdelay;
499 offset = pin->number;
500 if (offset > 32)
501 dev_err(serdes->dev, "%s offset=%d > 32\n",
502 serdes->dev->name, offset);
503 else
504 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n",
505 __func__, serdes->dev->name,
506 fdata->gpio_tx_id, fdata->gpio_rx_id, offset);
507
508 if (!ms) {
509 serdes_set_bits(serdes, GPIO_A_REG(offset),
510 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN | GPIO_OUT,
511 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
512 FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
513 FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en) |
514 FIELD_PREP(GPIO_OUT, fdata->gpio_out_level));
515 if (fdata->gpio_tx_en)
516 serdes_set_bits(serdes,
517 GPIO_B_REG(offset),
518 GPIO_TX_ID,
519 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
520 if (fdata->gpio_rx_en)
521 serdes_set_bits(serdes,
522 GPIO_C_REG(offset),
523 GPIO_RX_ID,
524 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
525 } else {
526 mdelay(ms);
527 SERDES_DBG_CHIP("%s: delay %dms\n", __func__, ms);
528 }
529 }
530
531 return 0;
532 }
533
max96772_pinctrl_set_grp_mux(struct serdes * serdes,unsigned int group_selector,unsigned int func_selector)534 static int max96772_pinctrl_set_grp_mux(struct serdes *serdes,
535 unsigned int group_selector,
536 unsigned int func_selector)
537 {
538 struct serdes_pinctrl *pinctrl = serdes->serdes_pinctrl;
539 struct function_desc *func;
540 struct group_desc *grp;
541 int i, offset;
542 u16 ms;
543
544 func = &serdes->chip_data->pinctrl_info->functions[func_selector];
545 if (!func) {
546 printf("%s: func is null\n", __func__);
547 return -EINVAL;
548 }
549
550 grp = &serdes->chip_data->pinctrl_info->groups[group_selector];
551 if (!grp) {
552 printf("%s: grp is null\n", __func__);
553 return -EINVAL;
554 }
555
556 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p grp=%s data=%p, num=%d\n",
557 __func__, serdes->chip_data->name, func->name,
558 func->data, grp->name, grp->data, grp->num_pins);
559
560 if (func->data) {
561 struct serdes_function_data *fdata = func->data;
562
563 ms = fdata->mdelay;
564 for (i = 0; i < grp->num_pins; i++) {
565 offset = grp->pins[i] - pinctrl->pin_base;
566 if (offset > 32)
567 dev_err(serdes->dev, "%s offset=%d > 32\n",
568 serdes->dev->name, offset);
569 else
570 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n",
571 __func__, serdes->dev->name,
572 fdata->gpio_tx_id, fdata->gpio_rx_id, offset);
573
574 if (!ms) {
575 serdes_set_bits(serdes, GPIO_A_REG(offset),
576 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN | GPIO_OUT,
577 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
578 FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
579 FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en) |
580 FIELD_PREP(GPIO_OUT, fdata->gpio_out_level));
581 if (fdata->gpio_tx_en)
582 serdes_set_bits(serdes,
583 GPIO_B_REG(offset),
584 GPIO_TX_ID,
585 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
586 if (fdata->gpio_rx_en)
587 serdes_set_bits(serdes,
588 GPIO_C_REG(offset),
589 GPIO_RX_ID,
590 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
591 } else {
592 mdelay(ms);
593 SERDES_DBG_CHIP("%s: delay %dms\n", __func__, ms);
594 }
595 }
596 }
597
598 if (grp->data) {
599 struct serdes_group_data *gdata = grp->data;
600
601 for (i = 0; i < gdata->num_configs; i++) {
602 const struct config_desc *config = &gdata->configs[i];
603 serdes_set_bits(serdes, config->reg,
604 config->mask, config->val);
605 }
606 }
607
608 return 0;
609 }
610
max96772_pinctrl_config_set(struct serdes * serdes,unsigned int pin_selector,unsigned int param,unsigned int argument)611 static int max96772_pinctrl_config_set(struct serdes *serdes,
612 unsigned int pin_selector,
613 unsigned int param,
614 unsigned int argument)
615 {
616 u8 res_cfg;
617
618 switch (param) {
619 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
620 serdes_set_bits(serdes, GPIO_B_REG(pin_selector),
621 OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
622 break;
623 case PIN_CONFIG_DRIVE_PUSH_PULL:
624 serdes_set_bits(serdes, GPIO_B_REG(pin_selector),
625 OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
626 break;
627 case PIN_CONFIG_BIAS_DISABLE:
628 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
629 PULL_UPDN_SEL,
630 FIELD_PREP(PULL_UPDN_SEL, 0));
631 break;
632 case PIN_CONFIG_BIAS_PULL_UP:
633 switch (argument) {
634 case 40000:
635 res_cfg = 0;
636 break;
637 case 1000000:
638 res_cfg = 1;
639 break;
640 default:
641 return -EINVAL;
642 }
643
644 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
645 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
646 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
647 PULL_UPDN_SEL,
648 FIELD_PREP(PULL_UPDN_SEL, 1));
649 break;
650 case PIN_CONFIG_BIAS_PULL_DOWN:
651 switch (argument) {
652 case 40000:
653 res_cfg = 0;
654 break;
655 case 1000000:
656 res_cfg = 1;
657 break;
658 default:
659 return -EINVAL;
660 }
661
662 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
663 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
664 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
665 PULL_UPDN_SEL,
666 FIELD_PREP(PULL_UPDN_SEL, 2));
667 break;
668 case PIN_CONFIG_OUTPUT:
669 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
670 GPIO_OUT_DIS | GPIO_OUT,
671 FIELD_PREP(GPIO_OUT_DIS, 0) |
672 FIELD_PREP(GPIO_OUT, argument));
673 break;
674 default:
675 return -EOPNOTSUPP;
676 }
677
678 return 0;
679 }
680
681 static struct serdes_chip_pinctrl_ops max96772_pinctrl_ops = {
682 .pinconf_set = max96772_pinctrl_config_set,
683 .pinmux_set = max96772_pinctrl_set_pin_mux,
684 .pinmux_group_set = max96772_pinctrl_set_grp_mux,
685 };
686
max96772_gpio_direction_input(struct serdes * serdes,int gpio)687 static int max96772_gpio_direction_input(struct serdes *serdes, int gpio)
688 {
689 return 0;
690 }
691
max96772_gpio_direction_output(struct serdes * serdes,int gpio,int value)692 static int max96772_gpio_direction_output(struct serdes *serdes,
693 int gpio, int value)
694 {
695 return 0;
696 }
697
max96772_gpio_get_level(struct serdes * serdes,int gpio)698 static int max96772_gpio_get_level(struct serdes *serdes, int gpio)
699 {
700 return 0;
701 }
702
max96772_gpio_set_level(struct serdes * serdes,int gpio,int value)703 static int max96772_gpio_set_level(struct serdes *serdes, int gpio, int value)
704 {
705 return 0;
706 }
707
max96772_gpio_set_config(struct serdes * serdes,int gpio,unsigned long config)708 static int max96772_gpio_set_config(struct serdes *serdes,
709 int gpio, unsigned long config)
710 {
711 return 0;
712 }
713
max96772_gpio_to_irq(struct serdes * serdes,int gpio)714 static int max96772_gpio_to_irq(struct serdes *serdes, int gpio)
715 {
716 return 0;
717 }
718
719 static struct serdes_chip_gpio_ops max96772_gpio_ops = {
720 .direction_input = max96772_gpio_direction_input,
721 .direction_output = max96772_gpio_direction_output,
722 .get_level = max96772_gpio_get_level,
723 .set_level = max96772_gpio_set_level,
724 .set_config = max96772_gpio_set_config,
725 .to_irq = max96772_gpio_to_irq,
726 };
727
728 struct serdes_chip_data serdes_max96772_data = {
729 .name = "max96772",
730 .serdes_type = TYPE_DES,
731 .serdes_id = MAXIM_ID_MAX96772,
732 .connector_type = DRM_MODE_CONNECTOR_eDP,
733 .pinctrl_info = &max96772_pinctrl_info,
734 .panel_ops = &max96772_panel_ops,
735 .pinctrl_ops = &max96772_pinctrl_ops,
736 .gpio_ops = &max96772_gpio_ops,
737 };
738 EXPORT_SYMBOL_GPL(serdes_max96772_data);
739
740 MODULE_LICENSE("GPL");
741