xref: /OK3568_Linux_fs/kernel/arch/parisc/kernel/head.S (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1/* This file is subject to the terms and conditions of the GNU General Public
2 * License.  See the file "COPYING" in the main directory of this archive
3 * for more details.
4 *
5 * Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de>
6 * Copyright 1999 SuSE GmbH (Philipp Rumpf)
7 * Copyright 1999 Philipp Rumpf (prumpf@tux.org)
8 * Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
9 * Copyright (C) 2001 Grant Grundler (Hewlett Packard)
10 * Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
11 *
12 * Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
13 */
14
15#include <asm/asm-offsets.h>
16#include <asm/psw.h>
17#include <asm/pdc.h>
18
19#include <asm/assembly.h>
20
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/pgtable.h>
24
25	.level	1.1
26
27	__INITDATA
28ENTRY(boot_args)
29	.word 0 /* arg0 */
30	.word 0 /* arg1 */
31	.word 0 /* arg2 */
32	.word 0 /* arg3 */
33END(boot_args)
34
35	__HEAD
36
37	.align	4
38	.import init_thread_union,data
39	.import fault_vector_20,code    /* IVA parisc 2.0 32 bit */
40#ifndef CONFIG_64BIT
41        .import fault_vector_11,code    /* IVA parisc 1.1 32 bit */
42	.import	$global$		/* forward declaration */
43#endif /*!CONFIG_64BIT*/
44ENTRY(parisc_kernel_start)
45	.proc
46	.callinfo
47
48	/* Make sure sr4-sr7 are set to zero for the kernel address space */
49	mtsp	%r0,%sr4
50	mtsp	%r0,%sr5
51	mtsp	%r0,%sr6
52	mtsp	%r0,%sr7
53
54	/* Clear BSS (shouldn't the boot loader do this?) */
55
56	.import __bss_start,data
57	.import __bss_stop,data
58
59	load32		PA(__bss_start),%r3
60	load32		PA(__bss_stop),%r4
61$bss_loop:
62	cmpb,<<,n       %r3,%r4,$bss_loop
63	stw,ma          %r0,4(%r3)
64
65	/* Save away the arguments the boot loader passed in (32 bit args) */
66	load32		PA(boot_args),%r1
67	stw,ma          %arg0,4(%r1)
68	stw,ma          %arg1,4(%r1)
69	stw,ma          %arg2,4(%r1)
70	stw,ma          %arg3,4(%r1)
71
72#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20)
73	/* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU
74	 * and halt kernel if we detect a PA1.x CPU. */
75	ldi		32,%r10
76	mtctl		%r10,%cr11
77	.level 2.0
78	mfctl,w		%cr11,%r10
79	.level 1.1
80	comib,<>,n	0,%r10,$cpu_ok
81
82	load32		PA(msg1),%arg0
83	ldi		msg1_end-msg1,%arg1
84$iodc_panic:
85	copy		%arg0, %r10
86	copy		%arg1, %r11
87	load32		PA(init_stack),%sp
88#define MEM_CONS 0x3A0
89	ldw		MEM_CONS+32(%r0),%arg0	// HPA
90	ldi		ENTRY_IO_COUT,%arg1
91	ldw		MEM_CONS+36(%r0),%arg2	// SPA
92	ldw		MEM_CONS+8(%r0),%arg3	// layers
93	load32		PA(__bss_start),%r1
94	stw		%r1,-52(%sp)		// arg4
95	stw		%r0,-56(%sp)		// arg5
96	stw		%r10,-60(%sp)		// arg6 = ptr to text
97	stw		%r11,-64(%sp)		// arg7 = len
98	stw		%r0,-68(%sp)		// arg8
99	load32		PA(.iodc_panic_ret), %rp
100	ldw		MEM_CONS+40(%r0),%r1	// ENTRY_IODC
101	bv,n		(%r1)
102.iodc_panic_ret:
103	b .				/* wait endless with ... */
104	or		%r10,%r10,%r10	/* qemu idle sleep */
105msg1:	.ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n"
106msg1_end:
107
108$cpu_ok:
109#endif
110
111	.level	PA_ASM_LEVEL
112
113	/* Initialize startup VM. Just map first 16/32 MB of memory */
114	load32		PA(swapper_pg_dir),%r4
115	mtctl		%r4,%cr24	/* Initialize kernel root pointer */
116	mtctl		%r4,%cr25	/* Initialize user root pointer */
117
118#if CONFIG_PGTABLE_LEVELS == 3
119	/* Set pmd in pgd */
120	load32		PA(pmd0),%r5
121	shrd            %r5,PxD_VALUE_SHIFT,%r3
122	ldo		(PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
123	stw		%r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
124	ldo		ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
125#else
126	/* 2-level page table, so pmd == pgd */
127	ldo		ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
128#endif
129
130	/* Fill in pmd with enough pte directories */
131	load32		PA(pg0),%r1
132	SHRREG		%r1,PxD_VALUE_SHIFT,%r3
133	ldo		(PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
134
135	ldi		ASM_PT_INITIAL,%r1
136
1371:
138	stw		%r3,0(%r4)
139	ldo		(PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
140	addib,>		-1,%r1,1b
141#if CONFIG_PGTABLE_LEVELS == 3
142	ldo             ASM_PMD_ENTRY_SIZE(%r4),%r4
143#else
144	ldo             ASM_PGD_ENTRY_SIZE(%r4),%r4
145#endif
146
147
148	/* Now initialize the PTEs themselves.  We use RWX for
149	 * everything ... it will get remapped correctly later */
150	ldo		0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
151	load32		(1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
152	load32		PA(pg0),%r1
153
154$pgt_fill_loop:
155	STREGM          %r3,ASM_PTE_ENTRY_SIZE(%r1)
156	ldo		(1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
157	addib,>		-1,%r11,$pgt_fill_loop
158	nop
159
160	/* Load the return address...er...crash 'n burn */
161	copy		%r0,%r2
162
163	/* And the RFI Target address too */
164	load32		start_parisc,%r11
165
166	/* And the initial task pointer */
167	load32		init_thread_union,%r6
168	mtctl           %r6,%cr30
169
170	/* And the stack pointer too */
171	ldo             THREAD_SZ_ALGN(%r6),%sp
172
173#if defined(CONFIG_64BIT) && defined(CONFIG_FUNCTION_TRACER)
174	.import _mcount,data
175	/* initialize mcount FPTR */
176	/* Get the global data pointer */
177	loadgp
178	load32		PA(_mcount), %r10
179	std		%dp,0x18(%r10)
180#endif
181
182#ifdef CONFIG_64BIT
183	/* Get PDCE_PROC for monarch CPU. */
184#define MEM_PDC_LO 0x388
185#define MEM_PDC_HI 0x35C
186	ldw             MEM_PDC_LO(%r0),%r3
187	ldw             MEM_PDC_HI(%r0),%r10
188	depd            %r10, 31, 32, %r3        /* move to upper word */
189#endif
190
191
192#ifdef CONFIG_SMP
193	/* Set the smp rendezvous address into page zero.
194	** It would be safer to do this in init_smp_config() but
195	** it's just way easier to deal with here because
196	** of 64-bit function ptrs and the address is local to this file.
197	*/
198	load32		PA(smp_slave_stext),%r10
199	stw		%r10,0x10(%r0)	/* MEM_RENDEZ */
200	stw		%r0,0x28(%r0)	/* MEM_RENDEZ_HI - assume addr < 4GB */
201
202	/* FALLTHROUGH */
203	.procend
204
205	/*
206	** Code Common to both Monarch and Slave processors.
207	** Entry:
208	**
209	**  1.1:
210	**    %r11 must contain RFI target address.
211	**    %r25/%r26 args to pass to target function
212	**    %r2  in case rfi target decides it didn't like something
213	**
214	**  2.0w:
215	**    %r3  PDCE_PROC address
216	**    %r11 RFI target address
217	**
218	** Caller must init: SR4-7, %sp, %r10, %cr24/25,
219	*/
220common_stext:
221	.proc
222	.callinfo
223#else
224	/* Clear PDC entry point - we won't use it */
225	stw		%r0,0x10(%r0)	/* MEM_RENDEZ */
226	stw		%r0,0x28(%r0)	/* MEM_RENDEZ_HI */
227#endif /*CONFIG_SMP*/
228
229#ifdef CONFIG_64BIT
230	tophys_r1	%sp
231
232	/* Save the rfi target address */
233	ldd             TI_TASK-THREAD_SZ_ALGN(%sp), %r10
234	tophys_r1       %r10
235	std             %r11,  TASK_PT_GR11(%r10)
236	/* Switch to wide mode Superdome doesn't support narrow PDC
237	** calls.
238	*/
2391:	mfia            %rp             /* clear upper part of pcoq */
240	ldo             2f-1b(%rp),%rp
241	depdi           0,31,32,%rp
242	bv              (%rp)
243	ssm             PSW_SM_W,%r0
244
245        /* Set Wide mode as the "Default" (eg for traps)
246        ** First trap occurs *right* after (or part of) rfi for slave CPUs.
247        ** Someday, palo might not do this for the Monarch either.
248        */
2492:
250	mfctl		%cr30,%r6		/* PCX-W2 firmware bug */
251
252	ldo             PDC_PSW(%r0),%arg0              /* 21 */
253	ldo             PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
254	ldo             PDC_PSW_WIDE_BIT(%r0),%arg2     /* 2 */
255	load32          PA(stext_pdc_ret), %rp
256	bv              (%r3)
257	copy            %r0,%arg3
258
259stext_pdc_ret:
260	mtctl		%r6,%cr30		/* restore task thread info */
261
262	/* restore rfi target address*/
263	ldd             TI_TASK-THREAD_SZ_ALGN(%sp), %r10
264	tophys_r1       %r10
265	ldd             TASK_PT_GR11(%r10), %r11
266	tovirt_r1       %sp
267#endif
268
269	/* PARANOID: clear user scratch/user space SR's */
270	mtsp	%r0,%sr0
271	mtsp	%r0,%sr1
272	mtsp	%r0,%sr2
273	mtsp	%r0,%sr3
274
275	/* Initialize Protection Registers */
276	mtctl	%r0,%cr8
277	mtctl	%r0,%cr9
278	mtctl	%r0,%cr12
279	mtctl	%r0,%cr13
280
281	/* Initialize the global data pointer */
282	loadgp
283
284	/* Set up our interrupt table.  HPMCs might not work after this!
285	 *
286	 * We need to install the correct iva for PA1.1 or PA2.0. The
287	 * following short sequence of instructions can determine this
288	 * (without being illegal on a PA1.1 machine).
289	 */
290#ifndef CONFIG_64BIT
291	ldi		32,%r10
292	mtctl		%r10,%cr11
293	.level 2.0
294	mfctl,w		%cr11,%r10
295	.level 1.1
296	comib,<>,n	0,%r10,$is_pa20
297	ldil		L%PA(fault_vector_11),%r10
298	b		$install_iva
299	ldo		R%PA(fault_vector_11)(%r10),%r10
300
301$is_pa20:
302	.level		PA_ASM_LEVEL /* restore 1.1 || 2.0w */
303#endif /*!CONFIG_64BIT*/
304	load32		PA(fault_vector_20),%r10
305
306$install_iva:
307	mtctl		%r10,%cr14
308
309	b		aligned_rfi  /* Prepare to RFI! Man all the cannons! */
310	nop
311
312	.align 128
313aligned_rfi:
314	pcxt_ssm_bug
315
316	copy		%r3, %arg0	/* PDCE_PROC for smp_callin() */
317
318	rsm		PSW_SM_QUIET,%r0	/* off troublesome PSW bits */
319	/* Don't need NOPs, have 8 compliant insn before rfi */
320
321	mtctl		%r0,%cr17	/* Clear IIASQ tail */
322	mtctl		%r0,%cr17	/* Clear IIASQ head */
323
324	/* Load RFI target into PC queue */
325	mtctl		%r11,%cr18	/* IIAOQ head */
326	ldo		4(%r11),%r11
327	mtctl		%r11,%cr18	/* IIAOQ tail */
328
329	load32		KERNEL_PSW,%r10
330	mtctl		%r10,%ipsw
331
332	/* Jump through hyperspace to Virt Mode */
333	rfi
334	nop
335
336	.procend
337
338#ifdef CONFIG_SMP
339
340	.import smp_init_current_idle_task,data
341	.import	smp_callin,code
342
343#ifndef CONFIG_64BIT
344smp_callin_rtn:
345        .proc
346	.callinfo
347	break	1,1		/*  Break if returned from start_secondary */
348	nop
349	nop
350        .procend
351#endif /*!CONFIG_64BIT*/
352
353/***************************************************************************
354* smp_slave_stext is executed by all non-monarch Processors when the Monarch
355* pokes the slave CPUs in smp.c:smp_boot_cpus().
356*
357* Once here, registers values are initialized in order to branch to virtual
358* mode. Once all available/eligible CPUs are in virtual mode, all are
359* released and start out by executing their own idle task.
360*****************************************************************************/
361smp_slave_stext:
362        .proc
363	.callinfo
364
365	/*
366	** Initialize Space registers
367	*/
368	mtsp	   %r0,%sr4
369	mtsp	   %r0,%sr5
370	mtsp	   %r0,%sr6
371	mtsp	   %r0,%sr7
372
373#ifdef CONFIG_64BIT
374	/*
375	 *  Enable Wide mode early, in case the task_struct for the idle
376	 *  task in smp_init_current_idle_task was allocated above 4GB.
377	 */
3781:	mfia            %rp             /* clear upper part of pcoq */
379	ldo             2f-1b(%rp),%rp
380	depdi           0,31,32,%rp
381	bv              (%rp)
382	ssm             PSW_SM_W,%r0
3832:
384#endif
385
386	/*  Initialize the SP - monarch sets up smp_init_current_idle_task */
387	load32		PA(smp_init_current_idle_task),%sp
388	LDREG		0(%sp),%sp	/* load task address */
389	tophys_r1	%sp
390	LDREG		TASK_THREAD_INFO(%sp),%sp
391	mtctl           %sp,%cr30       /* store in cr30 */
392	ldo             THREAD_SZ_ALGN(%sp),%sp
393
394	/* point CPU to kernel page tables */
395	load32		PA(swapper_pg_dir),%r4
396	mtctl		%r4,%cr24	/* Initialize kernel root pointer */
397	mtctl		%r4,%cr25	/* Initialize user root pointer */
398
399#ifdef CONFIG_64BIT
400	/* Setup PDCE_PROC entry */
401	copy            %arg0,%r3
402#else
403	/* Load RFI *return* address in case smp_callin bails */
404	load32		smp_callin_rtn,%r2
405#endif
406
407	/* Load RFI target address.  */
408	load32		smp_callin,%r11
409
410	/* ok...common code can handle the rest */
411	b		common_stext
412	nop
413
414	.procend
415#endif /* CONFIG_SMP */
416
417ENDPROC(parisc_kernel_start)
418
419#ifndef CONFIG_64BIT
420	.section .data..ro_after_init
421
422	.align	4
423	.export	$global$,data
424
425	.type	$global$,@object
426	.size	$global$,4
427$global$:
428	.word 0
429#endif /*!CONFIG_64BIT*/
430