1 /*
2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <malloc.h>
9 #include <syscon.h>
10 #include <asm/gpio.h>
11 #include <asm/arch-rockchip/clock.h>
12 #include <asm/arch/vendor.h>
13 #include <edid.h>
14 #include <dm/device.h>
15 #include <dm/of_access.h>
16 #include <dm/ofnode.h>
17 #include <dm/read.h>
18 #include <linux/hdmi.h>
19 #include <linux/media-bus-format.h>
20 #include <linux/dw_hdmi.h>
21 #include <asm/io.h>
22 #include "rockchip_bridge.h"
23 #include "rockchip_display.h"
24 #include "rockchip_crtc.h"
25 #include "rockchip_connector.h"
26 #include "dw_hdmi.h"
27 #include "rockchip_phy.h"
28
29 #define HDCP_PRIVATE_KEY_SIZE 280
30 #define HDCP_KEY_SHA_SIZE 20
31 #define HDMI_HDCP1X_ID 5
32 #define HDMI_EDID_BLOCK_LEN 128
33 /*
34 * Unless otherwise noted, entries in this table are 100% optimization.
35 * Values can be obtained from hdmi_compute_n() but that function is
36 * slow so we pre-compute values we expect to see.
37 *
38 * All 32k and 48k values are expected to be the same (due to the way
39 * the math works) for any rate that's an exact kHz.
40 */
41 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
42 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
43 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
44 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
45 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
46 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
47 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
48 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
49 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
50 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
51 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
52 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
53 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
54 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
55 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
56 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
57 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
58 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
59 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
60 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
61 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
62 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
63 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
64 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
65 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
66 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
67 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
68 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
69 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
70 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
71 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
72 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
73 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
74 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
75 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
76 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
78 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
79
80 /* For 297 MHz+ HDMI spec have some other rule for setting N */
81 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
82 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
83
84 /* End of table */
85 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
86 };
87
88 static const u16 csc_coeff_default[3][4] = {
89 { 0x2000, 0x0000, 0x0000, 0x0000 },
90 { 0x0000, 0x2000, 0x0000, 0x0000 },
91 { 0x0000, 0x0000, 0x2000, 0x0000 }
92 };
93
94 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
95 { 0x2000, 0x6926, 0x74fd, 0x010e },
96 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
97 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
98 };
99
100 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
101 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
102 { 0x2000, 0x3264, 0x0000, 0x7e6d },
103 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
104 };
105
106 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
107 { 0x2591, 0x1322, 0x074b, 0x0000 },
108 { 0x6535, 0x2000, 0x7acc, 0x0200 },
109 { 0x6acd, 0x7534, 0x2000, 0x0200 }
110 };
111
112 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
113 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
114 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
115 { 0x6756, 0x78ab, 0x2000, 0x0200 }
116 };
117
118 static const u16 csc_coeff_full_to_limited[3][4] = {
119 { 0x36f7, 0x0000, 0x0000, 0x0040 },
120 { 0x0000, 0x36f7, 0x0000, 0x0040 },
121 { 0x0000, 0x0000, 0x36f7, 0x0040 }
122 };
123
124 struct hdmi_vmode {
125 bool mdataenablepolarity;
126
127 unsigned int mpixelclock;
128 unsigned int mpixelrepetitioninput;
129 unsigned int mpixelrepetitionoutput;
130 unsigned int mtmdsclock;
131 };
132
133 struct hdmi_data_info {
134 unsigned int enc_in_bus_format;
135 unsigned int enc_out_bus_format;
136 unsigned int enc_in_encoding;
137 unsigned int enc_out_encoding;
138 unsigned int quant_range;
139 unsigned int pix_repet_factor;
140 struct hdmi_vmode video_mode;
141 };
142
143 struct dw_hdmi_phy_data {
144 enum dw_hdmi_phy_type type;
145 const char *name;
146 unsigned int gen;
147 bool has_svsret;
148 int (*configure)(struct dw_hdmi *hdmi,
149 const struct dw_hdmi_plat_data *pdata,
150 unsigned long mpixelclock);
151 };
152
153 struct hdcp_keys {
154 u8 KSV[8];
155 u8 devicekey[HDCP_PRIVATE_KEY_SIZE];
156 u8 sha1[HDCP_KEY_SHA_SIZE];
157 u8 seeds[2];
158 };
159
160 struct dw_hdmi_i2c {
161 u8 slave_reg;
162 bool is_regaddr;
163 bool is_segment;
164
165 unsigned int scl_high_ns;
166 unsigned int scl_low_ns;
167 };
168
169 struct dw_hdmi {
170 int id;
171 enum dw_hdmi_devtype dev_type;
172 unsigned int version;
173 struct hdmi_data_info hdmi_data;
174 struct hdmi_edid_data edid_data;
175 const struct dw_hdmi_plat_data *plat_data;
176 struct ddc_adapter adap;
177
178 int vic;
179 int io_width;
180
181 unsigned long bus_format;
182 bool cable_plugin;
183 bool sink_is_hdmi;
184 bool sink_has_audio;
185 bool force_output;
186 void *regs;
187 void *grf;
188 void *gpio_base;
189 struct dw_hdmi_i2c *i2c;
190
191 struct {
192 const struct dw_hdmi_phy_ops *ops;
193 const char *name;
194 void *data;
195 bool enabled;
196 } phy;
197
198 struct drm_display_mode previous_mode;
199
200 unsigned int sample_rate;
201 unsigned int audio_cts;
202 unsigned int audio_n;
203 bool audio_enable;
204 bool scramble_low_rates;
205
206 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
207 u8 (*read)(struct dw_hdmi *hdmi, int offset);
208
209 bool hdcp1x_enable;
210 bool output_bus_format_rgb;
211
212 struct gpio_desc hpd_gpiod;
213 };
214
dw_hdmi_writel(struct dw_hdmi * hdmi,u8 val,int offset)215 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
216 {
217 writel(val, hdmi->regs + (offset << 2));
218 }
219
dw_hdmi_readl(struct dw_hdmi * hdmi,int offset)220 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
221 {
222 return readl(hdmi->regs + (offset << 2));
223 }
224
dw_hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)225 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
226 {
227 writeb(val, hdmi->regs + offset);
228 }
229
dw_hdmi_readb(struct dw_hdmi * hdmi,int offset)230 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
231 {
232 return readb(hdmi->regs + offset);
233 }
234
hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)235 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
236 {
237 hdmi->write(hdmi, val, offset);
238 }
239
hdmi_readb(struct dw_hdmi * hdmi,int offset)240 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
241 {
242 return hdmi->read(hdmi, offset);
243 }
244
hdmi_modb(struct dw_hdmi * hdmi,u8 data,u8 mask,unsigned reg)245 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
246 {
247 u8 val = hdmi_readb(hdmi, reg) & ~mask;
248
249 val |= data & mask;
250 hdmi_writeb(hdmi, val, reg);
251 }
252
hdmi_mask_writeb(struct dw_hdmi * hdmi,u8 data,unsigned int reg,u8 shift,u8 mask)253 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
254 u8 shift, u8 mask)
255 {
256 hdmi_modb(hdmi, data << shift, mask, reg);
257 }
258
hdmi_bus_fmt_is_rgb(unsigned int bus_format)259 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
260 {
261 switch (bus_format) {
262 case MEDIA_BUS_FMT_RGB888_1X24:
263 case MEDIA_BUS_FMT_RGB101010_1X30:
264 case MEDIA_BUS_FMT_RGB121212_1X36:
265 case MEDIA_BUS_FMT_RGB161616_1X48:
266 return true;
267
268 default:
269 return false;
270 }
271 }
272
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)273 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
274 {
275 switch (bus_format) {
276 case MEDIA_BUS_FMT_YUV8_1X24:
277 case MEDIA_BUS_FMT_YUV10_1X30:
278 case MEDIA_BUS_FMT_YUV12_1X36:
279 case MEDIA_BUS_FMT_YUV16_1X48:
280 return true;
281
282 default:
283 return false;
284 }
285 }
286
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)287 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
288 {
289 switch (bus_format) {
290 case MEDIA_BUS_FMT_UYVY8_1X16:
291 case MEDIA_BUS_FMT_UYVY10_1X20:
292 case MEDIA_BUS_FMT_UYVY12_1X24:
293 return true;
294
295 default:
296 return false;
297 }
298 }
299
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)300 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
301 {
302 switch (bus_format) {
303 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
304 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
305 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
306 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
307 return true;
308
309 default:
310 return false;
311 }
312 }
313
hdmi_bus_fmt_color_depth(unsigned int bus_format)314 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
315 {
316 switch (bus_format) {
317 case MEDIA_BUS_FMT_RGB888_1X24:
318 case MEDIA_BUS_FMT_YUV8_1X24:
319 case MEDIA_BUS_FMT_UYVY8_1X16:
320 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
321 return 8;
322
323 case MEDIA_BUS_FMT_RGB101010_1X30:
324 case MEDIA_BUS_FMT_YUV10_1X30:
325 case MEDIA_BUS_FMT_UYVY10_1X20:
326 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
327 return 10;
328
329 case MEDIA_BUS_FMT_RGB121212_1X36:
330 case MEDIA_BUS_FMT_YUV12_1X36:
331 case MEDIA_BUS_FMT_UYVY12_1X24:
332 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
333 return 12;
334
335 case MEDIA_BUS_FMT_RGB161616_1X48:
336 case MEDIA_BUS_FMT_YUV16_1X48:
337 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
338 return 16;
339
340 default:
341 return 0;
342 }
343 }
344
is_color_space_conversion(struct dw_hdmi * hdmi)345 static int is_color_space_conversion(struct dw_hdmi *hdmi)
346 {
347 struct drm_display_mode *mode =
348 hdmi->edid_data.preferred_mode;
349 bool is_cea_default;
350
351 is_cea_default = (drm_match_cea_mode(mode) > 1) &&
352 (hdmi->hdmi_data.quant_range ==
353 HDMI_QUANTIZATION_RANGE_DEFAULT);
354
355 /*
356 * When output is rgb limited range or default range with
357 * cea mode, csc should be enabled.
358 */
359 if (hdmi->hdmi_data.enc_in_bus_format !=
360 hdmi->hdmi_data.enc_out_bus_format ||
361 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED ||
362 is_cea_default) &&
363 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format)))
364 return 1;
365
366 return 0;
367 }
368
is_color_space_decimation(struct dw_hdmi * hdmi)369 static int is_color_space_decimation(struct dw_hdmi *hdmi)
370 {
371 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
372 return 0;
373
374 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
375 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
376 return 1;
377
378 return 0;
379 }
380
hdmi_phy_test_clear(struct dw_hdmi * hdmi,unsigned char bit)381 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
382 unsigned char bit)
383 {
384 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
385 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
386 }
387
hdmi_phy_test_enable(struct dw_hdmi * hdmi,unsigned char bit)388 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
389 unsigned char bit)
390 {
391 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
392 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
393 }
394
hdmi_phy_test_clock(struct dw_hdmi * hdmi,unsigned char bit)395 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
396 unsigned char bit)
397 {
398 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
399 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
400 }
401
hdmi_phy_test_din(struct dw_hdmi * hdmi,unsigned char bit)402 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
403 unsigned char bit)
404 {
405 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
406 }
407
hdmi_phy_test_dout(struct dw_hdmi * hdmi,unsigned char bit)408 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
409 unsigned char bit)
410 {
411 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
412 }
413
dw_hdmi_i2c_read(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)414 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
415 unsigned char *buf, unsigned int length)
416 {
417 struct dw_hdmi_i2c *i2c = hdmi->i2c;
418 int interrupt = 0, i = 20;
419 bool read_edid = false;
420
421 if (!i2c->is_regaddr) {
422 printf("set read register address to 0\n");
423 i2c->slave_reg = 0x00;
424 i2c->is_regaddr = true;
425 }
426
427 /* edid reads are in 128 bytes. scdc reads are in 1 byte */
428 if (length == HDMI_EDID_BLOCK_LEN)
429 read_edid = true;
430
431 while (length > 0) {
432 hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
433
434 if (read_edid) {
435 i2c->slave_reg += 8;
436 length -= 8;
437 } else {
438 i2c->slave_reg++;
439 length--;
440 }
441
442 if (i2c->is_segment) {
443 if (read_edid)
444 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
445 HDMI_I2CM_OPERATION);
446 else
447 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
448 HDMI_I2CM_OPERATION);
449 } else {
450 if (read_edid)
451 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
452 HDMI_I2CM_OPERATION);
453 else
454 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
455 HDMI_I2CM_OPERATION);
456 }
457
458 while (i--) {
459 udelay(1000);
460 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
461 if (interrupt)
462 hdmi_writeb(hdmi, interrupt,
463 HDMI_IH_I2CM_STAT0);
464 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE |
465 m_I2CM_ERROR))
466 break;
467 }
468
469 if (!interrupt) {
470 printf("[%s] i2c read reg[0x%02x] no interrupt\n",
471 __func__, i2c->slave_reg);
472 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
473 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
474 HDMI_I2CM_OPERATION);
475 udelay(1000);
476 return -EAGAIN;
477 }
478
479 /* Check for error condition on the bus */
480 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) {
481 printf("[%s] read reg[0x%02x] data error:0x%02x\n",
482 __func__, i2c->slave_reg, interrupt);
483 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
484 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
485 HDMI_I2CM_OPERATION);
486 udelay(1000);
487 return -EIO;
488 }
489
490 i = 20;
491 if (read_edid)
492 for (i = 0; i < 8; i++)
493 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
494 else
495 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
496 }
497 i2c->is_segment = false;
498
499 return 0;
500 }
501
dw_hdmi_i2c_write(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)502 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
503 unsigned char *buf, unsigned int length)
504 {
505 struct dw_hdmi_i2c *i2c = hdmi->i2c;
506 int i = 20;
507 u8 interrupt = 0;
508
509 if (!i2c->is_regaddr) {
510 /* Use the first write byte as register address */
511 i2c->slave_reg = buf[0];
512 length--;
513 buf++;
514 i2c->is_regaddr = true;
515 }
516
517 while (length--) {
518 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
519 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
520 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
521 HDMI_I2CM_OPERATION);
522
523 while (i--) {
524 udelay(1000);
525 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
526 if (interrupt)
527 hdmi_writeb(hdmi,
528 interrupt, HDMI_IH_I2CM_STAT0);
529
530 if (interrupt & (m_SCDC_READREQ |
531 m_I2CM_DONE | m_I2CM_ERROR))
532 break;
533 }
534
535 if (!interrupt) {
536 printf("[%s] i2c write reg[0x%02x] no interrupt\n",
537 __func__, i2c->slave_reg);
538 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
539 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
540 HDMI_I2CM_OPERATION);
541 udelay(1000);
542 return -EAGAIN;
543 }
544
545 if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
546 printf("[%s] write data error\n", __func__);
547 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
548 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
549 HDMI_I2CM_OPERATION);
550 udelay(1000);
551 return -EIO;
552 } else if (interrupt & m_I2CM_DONE) {
553 printf("[%s] write offset %02x success\n",
554 __func__, i2c->slave_reg);
555 return -EAGAIN;
556 }
557
558 i = 20;
559 }
560
561 return 0;
562 }
563
dw_hdmi_i2c_xfer(struct ddc_adapter * adap,struct i2c_msg * msgs,int num)564 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap,
565 struct i2c_msg *msgs, int num)
566 {
567 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap);
568 struct dw_hdmi_i2c *i2c = hdmi->i2c;
569 u8 addr = msgs[0].addr;
570 int i, ret = 0;
571
572 printf("xfer: num: %d, addr: %#x\n", num, addr);
573 for (i = 0; i < num; i++) {
574 if (msgs[i].len == 0) {
575 printf("unsupported transfer %d/%d, no data\n",
576 i + 1, num);
577 return -EOPNOTSUPP;
578 }
579 }
580
581 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
582
583 /* Set slave device address taken from the first I2C message */
584 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
585 addr = DDC_ADDR;
586 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
587
588 /* Set slave device register address on transfer */
589 i2c->is_regaddr = false;
590
591 /* Set segment pointer for I2C extended read mode operation */
592 i2c->is_segment = false;
593
594 for (i = 0; i < num; i++) {
595 debug("xfer: num: %d/%d, len: %d, flags: %#x\n",
596 i + 1, num, msgs[i].len, msgs[i].flags);
597 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
598 i2c->is_segment = true;
599 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
600 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
601 } else {
602 if (msgs[i].flags & I2C_M_RD)
603 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
604 msgs[i].len);
605 else
606 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
607 msgs[i].len);
608 }
609 if (ret < 0)
610 break;
611 }
612
613 if (!ret)
614 ret = num;
615
616 /* Mute DONE and ERROR interrupts */
617 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
618 HDMI_IH_MUTE_I2CM_STAT0);
619
620 return ret;
621 }
622
hdmi_phy_wait_i2c_done(struct dw_hdmi * hdmi,int msec)623 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
624 {
625 u32 val;
626
627 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
628 if (msec-- == 0)
629 return false;
630 udelay(1000);
631 }
632 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
633
634 return true;
635 }
636
dw_hdmi_phy_i2c_write(struct dw_hdmi * hdmi,unsigned short data,unsigned char addr)637 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
638 unsigned char addr)
639 {
640 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
641 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
642 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
643 HDMI_PHY_I2CM_DATAO_1_ADDR);
644 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
645 HDMI_PHY_I2CM_DATAO_0_ADDR);
646 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
647 HDMI_PHY_I2CM_OPERATION_ADDR);
648 hdmi_phy_wait_i2c_done(hdmi, 1000);
649 }
650
dw_hdmi_phy_enable_powerdown(struct dw_hdmi * hdmi,bool enable)651 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
652 {
653 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
654 HDMI_PHY_CONF0_PDZ_OFFSET,
655 HDMI_PHY_CONF0_PDZ_MASK);
656 }
657
dw_hdmi_phy_enable_tmds(struct dw_hdmi * hdmi,u8 enable)658 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
659 {
660 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
661 HDMI_PHY_CONF0_ENTMDS_OFFSET,
662 HDMI_PHY_CONF0_ENTMDS_MASK);
663 }
664
dw_hdmi_phy_enable_svsret(struct dw_hdmi * hdmi,u8 enable)665 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
666 {
667 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
668 HDMI_PHY_CONF0_SVSRET_OFFSET,
669 HDMI_PHY_CONF0_SVSRET_MASK);
670 }
671
dw_hdmi_phy_gen2_pddq(struct dw_hdmi * hdmi,u8 enable)672 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
673 {
674 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
675 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
676 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
677 }
678
dw_hdmi_phy_gen2_txpwron(struct dw_hdmi * hdmi,u8 enable)679 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
680 {
681 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
682 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
683 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
684 }
685
dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi * hdmi,u8 enable)686 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
687 {
688 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
689 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
690 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
691 }
692
dw_hdmi_phy_sel_interface_control(struct dw_hdmi * hdmi,u8 enable)693 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
694 {
695 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
696 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
697 HDMI_PHY_CONF0_SELDIPIF_MASK);
698 }
699
dw_hdmi_phy_power_off(struct dw_hdmi * hdmi)700 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
701 {
702 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
703 unsigned int i;
704 u16 val;
705
706 if (phy->gen == 1) {
707 dw_hdmi_phy_enable_tmds(hdmi, 0);
708 dw_hdmi_phy_enable_powerdown(hdmi, true);
709 return;
710 }
711
712 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
713
714 /*
715 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
716 * to low power mode.
717 */
718 for (i = 0; i < 5; ++i) {
719 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
720 if (!(val & HDMI_PHY_TX_PHY_LOCK))
721 break;
722
723 udelay(2000);
724 }
725
726 if (val & HDMI_PHY_TX_PHY_LOCK)
727 printf("PHY failed to power down\n");
728 else
729 printf("PHY powered down in %u iterations\n", i);
730
731 dw_hdmi_phy_gen2_pddq(hdmi, 1);
732 }
733
dw_hdmi_phy_power_on(struct dw_hdmi * hdmi)734 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
735 {
736 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
737 unsigned int i;
738 u8 val;
739
740 if (phy->gen == 1) {
741 dw_hdmi_phy_enable_powerdown(hdmi, false);
742
743 /* Toggle TMDS enable. */
744 dw_hdmi_phy_enable_tmds(hdmi, 0);
745 dw_hdmi_phy_enable_tmds(hdmi, 1);
746 return 0;
747 }
748
749 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
750 dw_hdmi_phy_gen2_pddq(hdmi, 0);
751
752 /* Wait for PHY PLL lock */
753 for (i = 0; i < 5; ++i) {
754 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
755 if (val)
756 break;
757
758 udelay(2000);
759 }
760
761 if (!val) {
762 printf("PHY PLL failed to lock\n");
763 return -ETIMEDOUT;
764 }
765 printf("PHY PLL locked %u iterations\n", i);
766
767 return 0;
768 }
769
770 /*
771 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
772 * information the DWC MHL PHY has the same register layout and is thus also
773 * supported by this function.
774 */
775 static
hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi * hdmi,const struct dw_hdmi_plat_data * pdata,unsigned long mpixelclock)776 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
777 const struct dw_hdmi_plat_data *pdata,
778 unsigned long mpixelclock)
779 {
780 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
781 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
782 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
783 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
784 unsigned int depth =
785 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
786
787 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
788 pdata->mpll_cfg_420)
789 mpll_config = pdata->mpll_cfg_420;
790
791 /* PLL/MPLL Cfg - always match on final entry */
792 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
793 if (mpixelclock <= mpll_config->mpixelclock)
794 break;
795
796 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
797 if (tmdsclock <= curr_ctrl->mpixelclock)
798 break;
799
800 for (; phy_config->mpixelclock != ~0UL; phy_config++)
801 if (tmdsclock <= phy_config->mpixelclock)
802 break;
803
804 if (mpll_config->mpixelclock == ~0UL ||
805 curr_ctrl->mpixelclock == ~0UL ||
806 phy_config->mpixelclock == ~0UL)
807 return -EINVAL;
808
809 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
810 depth = fls(depth - 8);
811 else
812 depth = 0;
813 if (depth)
814 depth--;
815
816 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce,
817 HDMI_3D_TX_PHY_CPCE_CTRL);
818
819 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp,
820 HDMI_3D_TX_PHY_GMPCTRL);
821 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth],
822 HDMI_3D_TX_PHY_CURRCTRL);
823
824 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
825 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
826 HDMI_3D_TX_PHY_MSM_CTRL);
827
828 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
829 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
830 HDMI_3D_TX_PHY_CKSYMTXCTRL);
831 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
832 HDMI_3D_TX_PHY_VLEVCTRL);
833
834 return 0;
835 }
836
837 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
838 {
839 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
840 .name = "DWC HDMI TX PHY",
841 .gen = 1,
842 }, {
843 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
844 .name = "DWC MHL PHY + HEAC PHY",
845 .gen = 2,
846 .has_svsret = true,
847 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
848 }, {
849 .type = DW_HDMI_PHY_DWC_MHL_PHY,
850 .name = "DWC MHL PHY",
851 .gen = 2,
852 .has_svsret = true,
853 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
854 }, {
855 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
856 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
857 .gen = 2,
858 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
859 }, {
860 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
861 .name = "DWC HDMI 3D TX PHY",
862 .gen = 2,
863 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
864 }, {
865 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
866 .name = "DWC HDMI 2.0 TX PHY",
867 .gen = 2,
868 .has_svsret = true,
869 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
870 }, {
871 .type = DW_HDMI_PHY_VENDOR_PHY,
872 .name = "Vendor PHY",
873 }
874 };
875
rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi * hdmi,int enable)876 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi,
877 int enable)
878 {
879 u8 stat;
880
881 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat);
882
883 if (stat < 0 && !hdmi->force_output) {
884 debug("Failed to read tmds config\n");
885 return false;
886 }
887
888 if (enable == 1) {
889 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
890 stat |= SCDC_SCRAMBLING_ENABLE;
891 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
892 /* TMDS software reset request */
893 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
894 HDMI_MC_SWRSTZ);
895 /* Enable/Disable Scrambling */
896 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
897 } else {
898 /* Enable/Disable Scrambling */
899 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
900 /* TMDS software reset request */
901 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
902 HDMI_MC_SWRSTZ);
903 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
904 stat &= ~SCDC_SCRAMBLING_ENABLE;
905 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
906 }
907
908 return 0;
909 }
910
rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi * hdmi)911 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi)
912 {
913 u8 stat;
914
915 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat);
916 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000)
917 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
918 else
919 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
920 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
921 }
922
hdmi_phy_configure(struct dw_hdmi * hdmi)923 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
924 {
925 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
926 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
927 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
928 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
929 int ret;
930
931 dw_hdmi_phy_power_off(hdmi);
932
933 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
934 if (hdmi->edid_data.display_info.hdmi.scdc.supported)
935 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi);
936
937 /* Leave low power consumption mode by asserting SVSRET. */
938 if (phy->has_svsret)
939 dw_hdmi_phy_enable_svsret(hdmi, 1);
940
941 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
942 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
943 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
944
945 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
946
947 hdmi_phy_test_clear(hdmi, 1);
948 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
949 HDMI_PHY_I2CM_SLAVE_ADDR);
950 hdmi_phy_test_clear(hdmi, 0);
951
952 /* Write to the PHY as configured by the platform */
953 if (pdata->configure_phy)
954 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
955 else
956 ret = phy->configure(hdmi, pdata, mpixelclock);
957 if (ret) {
958 printf("PHY configuration failed (clock %lu)\n",
959 mpixelclock);
960 return ret;
961 }
962
963 /* Wait for resuming transmission of TMDS clock and data */
964 if (mtmdsclock > 340000000)
965 mdelay(100);
966
967 return dw_hdmi_phy_power_on(hdmi);
968 }
969
dw_hdmi_phy_init(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)970 static int dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
971 void *data)
972 {
973 int i, ret;
974
975 /* HDMI Phy spec says to do the phy initialization sequence twice */
976 for (i = 0; i < 2; i++) {
977 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
978 dw_hdmi_phy_sel_interface_control(hdmi, 0);
979 ret = hdmi_phy_configure(hdmi);
980 if (ret)
981 return ret;
982 }
983
984 return 0;
985 }
986
dw_hdmi_phy_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)987 static void dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
988 void *data)
989 {
990 dw_hdmi_phy_power_off(hdmi);
991 }
992
993 static enum drm_connector_status
dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)994 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)
995 {
996 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
997 connector_status_connected : connector_status_disconnected;
998 }
999
1000 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1001 .init = dw_hdmi_phy_init,
1002 .disable = dw_hdmi_phy_disable,
1003 .read_hpd = dw_hdmi_phy_read_hpd,
1004 };
1005
dw_hdmi_detect_phy(struct dw_hdmi * hdmi)1006 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
1007 {
1008 unsigned int i;
1009 u8 phy_type;
1010
1011 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
1012
1013 /*
1014 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
1015 * but it has a vedor phy.
1016 */
1017 if (phy_type == DW_HDMI_PHY_VENDOR_PHY ||
1018 hdmi->dev_type == RK3528_HDMI ||
1019 hdmi->dev_type == RK3328_HDMI ||
1020 hdmi->dev_type == RK3228_HDMI) {
1021 /* Vendor PHYs require support from the glue layer. */
1022 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
1023 printf(
1024 "Vendor HDMI PHY not supported by glue layer\n");
1025 return -ENODEV;
1026 }
1027
1028 hdmi->phy.ops = hdmi->plat_data->phy_ops;
1029 hdmi->phy.data = hdmi->plat_data->phy_data;
1030 hdmi->phy.name = hdmi->plat_data->phy_name;
1031 return 0;
1032 }
1033
1034 /* Synopsys PHYs are handled internally. */
1035 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
1036 if (dw_hdmi_phys[i].type == phy_type) {
1037 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
1038 hdmi->phy.name = dw_hdmi_phys[i].name;
1039 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
1040
1041 if (!dw_hdmi_phys[i].configure &&
1042 !hdmi->plat_data->configure_phy) {
1043 printf("%s requires platform support\n",
1044 hdmi->phy.name);
1045 return -ENODEV;
1046 }
1047
1048 return 0;
1049 }
1050 }
1051
1052 printf("Unsupported HDMI PHY type (%02x)\n", phy_type);
1053 return -ENODEV;
1054 }
1055
1056 static unsigned int
hdmi_get_tmdsclock(struct dw_hdmi * hdmi,unsigned long mpixelclock)1057 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
1058 {
1059 unsigned int tmdsclock = mpixelclock;
1060 unsigned int depth =
1061 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1062
1063 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1064 switch (depth) {
1065 case 16:
1066 tmdsclock = mpixelclock * 2;
1067 break;
1068 case 12:
1069 tmdsclock = mpixelclock * 3 / 2;
1070 break;
1071 case 10:
1072 tmdsclock = mpixelclock * 5 / 4;
1073 break;
1074 default:
1075 break;
1076 }
1077 }
1078
1079 return tmdsclock;
1080 }
1081
hdmi_av_composer(struct dw_hdmi * hdmi,const struct drm_display_mode * mode)1082 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1083 const struct drm_display_mode *mode)
1084 {
1085 u8 bytes = 0, inv_val = 0;
1086 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1087 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi;
1088 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1089 unsigned int hdisplay, vdisplay;
1090
1091 vmode->mpixelclock = mode->crtc_clock * 1000;
1092 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1093 DRM_MODE_FLAG_3D_FRAME_PACKING)
1094 vmode->mpixelclock *= 2;
1095 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1096 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1097 vmode->mtmdsclock /= 2;
1098 printf("final pixclk = %d tmdsclk = %d\n",
1099 vmode->mpixelclock, vmode->mtmdsclock);
1100
1101 /* Set up HDMI_FC_INVIDCONF
1102 * Some display equipments require that the interval
1103 * between Video Data and Data island must be at least 58 pixels,
1104 * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement.
1105 */
1106 inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE;
1107
1108 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1109 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1110 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1111
1112 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1113 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1114 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1115
1116 inv_val |= (vmode->mdataenablepolarity ?
1117 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1118 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1119
1120 if (hdmi->vic == 39)
1121 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1122 else
1123 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1124 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1125 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1126
1127 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1128 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1129 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1130
1131 inv_val |= hdmi->sink_is_hdmi ?
1132 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1133 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1134
1135 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1136
1137 hdisplay = mode->hdisplay;
1138 hblank = mode->htotal - mode->hdisplay;
1139 h_de_hs = mode->hsync_start - mode->hdisplay;
1140 hsync_len = mode->hsync_end - mode->hsync_start;
1141
1142 /*
1143 * When we're setting a YCbCr420 mode, we need
1144 * to adjust the horizontal timing to suit.
1145 */
1146 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1147 hdisplay /= 2;
1148 hblank /= 2;
1149 h_de_hs /= 2;
1150 hsync_len /= 2;
1151 }
1152
1153 vdisplay = mode->vdisplay;
1154 vblank = mode->vtotal - mode->vdisplay;
1155 v_de_vs = mode->vsync_start - mode->vdisplay;
1156 vsync_len = mode->vsync_end - mode->vsync_start;
1157
1158 /*
1159 * When we're setting an interlaced mode, we need
1160 * to adjust the vertical timing to suit.
1161 */
1162 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1163 vdisplay /= 2;
1164 vblank /= 2;
1165 v_de_vs /= 2;
1166 vsync_len /= 2;
1167 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1168 DRM_MODE_FLAG_3D_FRAME_PACKING) {
1169 vdisplay += mode->vtotal;
1170 }
1171
1172 /* Scrambling Control */
1173 if (hdmi_info->scdc.supported || hdmi->force_output) {
1174 if (vmode->mtmdsclock > 340000000 ||
1175 (hdmi_info->scdc.scrambling.low_rates &&
1176 hdmi->scramble_low_rates)) {
1177 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes);
1178 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION,
1179 bytes);
1180 rockchip_dw_hdmi_scrambling_enable(hdmi, 1);
1181 } else {
1182 rockchip_dw_hdmi_scrambling_enable(hdmi, 0);
1183 }
1184 }
1185
1186 /* Set up horizontal active pixel width */
1187 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1188 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1189
1190 /* Set up vertical active lines */
1191 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1192 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1193
1194 /* Set up horizontal blanking pixel region width */
1195 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1196 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1197
1198 /* Set up vertical blanking pixel region width */
1199 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1200
1201 /* Set up HSYNC active edge delay width (in pixel clks) */
1202 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1203 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1204
1205 /* Set up VSYNC active edge delay (in lines) */
1206 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1207
1208 /* Set up HSYNC active pulse width (in pixel clks) */
1209 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1210 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1211
1212 /* Set up VSYNC active edge delay (in lines) */
1213 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1214 }
1215
dw_hdmi_update_csc_coeffs(struct dw_hdmi * hdmi)1216 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1217 {
1218 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1219 unsigned i;
1220 u32 csc_scale = 1;
1221 int enc_out_rgb, enc_in_rgb;
1222
1223 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1224 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1225
1226 if (is_color_space_conversion(hdmi)) {
1227 if (enc_out_rgb && enc_in_rgb) {
1228 csc_coeff = &csc_coeff_full_to_limited;
1229 csc_scale = 0;
1230 } else if (enc_out_rgb) {
1231 if (hdmi->hdmi_data.enc_out_encoding ==
1232 V4L2_YCBCR_ENC_601)
1233 csc_coeff = &csc_coeff_rgb_out_eitu601;
1234 else
1235 csc_coeff = &csc_coeff_rgb_out_eitu709;
1236 } else if (enc_in_rgb) {
1237 if (hdmi->hdmi_data.enc_out_encoding ==
1238 V4L2_YCBCR_ENC_601)
1239 csc_coeff = &csc_coeff_rgb_in_eitu601;
1240 else
1241 csc_coeff = &csc_coeff_rgb_in_eitu709;
1242 csc_scale = 0;
1243 }
1244 }
1245
1246 /* The CSC registers are sequential, alternating MSB then LSB */
1247 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1248 u16 coeff_a = (*csc_coeff)[0][i];
1249 u16 coeff_b = (*csc_coeff)[1][i];
1250 u16 coeff_c = (*csc_coeff)[2][i];
1251
1252 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1253 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1254 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1255 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1256 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1257 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1258 }
1259
1260 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1261 HDMI_CSC_SCALE);
1262 }
1263
is_color_space_interpolation(struct dw_hdmi * hdmi)1264 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1265 {
1266 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1267 return 0;
1268
1269 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1270 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1271 return 1;
1272
1273 return 0;
1274 }
1275
hdmi_video_csc(struct dw_hdmi * hdmi)1276 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1277 {
1278 int color_depth = 0;
1279 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1280 int decimation = 0;
1281
1282 /* YCC422 interpolation to 444 mode */
1283 if (is_color_space_interpolation(hdmi))
1284 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1285 else if (is_color_space_decimation(hdmi))
1286 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1287
1288 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1289 case 8:
1290 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1291 break;
1292 case 10:
1293 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1294 break;
1295 case 12:
1296 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1297 break;
1298 case 16:
1299 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1300 break;
1301
1302 default:
1303 return;
1304 }
1305
1306 /* Configure the CSC registers */
1307 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1308 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1309 HDMI_CSC_SCALE);
1310
1311 dw_hdmi_update_csc_coeffs(hdmi);
1312 }
1313
dw_hdmi_enable_video_path(struct dw_hdmi * hdmi)1314 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1315 {
1316 u8 clkdis;
1317
1318 /* control period minimum duration */
1319 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1320 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1321 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1322
1323 /* Set to fill TMDS data channels */
1324 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1325 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1326 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1327
1328 /* Enable pixel clock and tmds data path */
1329 clkdis = 0x7F;
1330 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1331 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1332
1333 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1334 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1335
1336 /* Enable csc path */
1337 if (is_color_space_conversion(hdmi)) {
1338 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1339 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1340 }
1341
1342 /* Enable pixel repetition path */
1343 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1344 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1345 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1346 }
1347
1348 /* Enable color space conversion if needed */
1349 if (is_color_space_conversion(hdmi))
1350 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1351 HDMI_MC_FLOWCTRL);
1352 else
1353 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1354 HDMI_MC_FLOWCTRL);
1355 }
1356
dw_hdmi_clear_overflow(struct dw_hdmi * hdmi)1357 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1358 {
1359 unsigned int count;
1360 unsigned int i;
1361 u8 val;
1362
1363 /*
1364 * Under some circumstances the Frame Composer arithmetic unit can miss
1365 * an FC register write due to being busy processing the previous one.
1366 * The issue can be worked around by issuing a TMDS software reset and
1367 * then write one of the FC registers several times.
1368 *
1369 * The number of iterations matters and depends on the HDMI TX revision
1370 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1371 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1372 * 4 and 1 iterations respectively.
1373 */
1374
1375 switch (hdmi->version) {
1376 case 0x130a:
1377 count = 4;
1378 break;
1379 case 0x131a:
1380 case 0x200a:
1381 case 0x201a:
1382 case 0x211a:
1383 count = 1;
1384 break;
1385 default:
1386 return;
1387 }
1388
1389 /* TMDS software reset */
1390 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1391
1392 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1393 for (i = 0; i < count; i++)
1394 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1395 }
1396
hdmi_disable_overflow_interrupts(struct dw_hdmi * hdmi)1397 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1398 {
1399 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1400 HDMI_IH_MUTE_FC_STAT2);
1401 }
1402
hdmi_video_packetize(struct dw_hdmi * hdmi)1403 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1404 {
1405 unsigned int color_depth = 0;
1406 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1407 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1408 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1409 u8 val, vp_conf;
1410
1411 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1412 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1413 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1414 switch (hdmi_bus_fmt_color_depth(
1415 hdmi->hdmi_data.enc_out_bus_format)) {
1416 case 8:
1417 color_depth = 0;
1418 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1419 break;
1420 case 10:
1421 color_depth = 5;
1422 break;
1423 case 12:
1424 color_depth = 6;
1425 break;
1426 case 16:
1427 color_depth = 7;
1428 break;
1429 default:
1430 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1431 }
1432 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1433 switch (hdmi_bus_fmt_color_depth(
1434 hdmi->hdmi_data.enc_out_bus_format)) {
1435 case 0:
1436 case 8:
1437 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1438 break;
1439 case 10:
1440 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1441 break;
1442 case 12:
1443 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1444 break;
1445
1446 default:
1447 return;
1448 }
1449 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1450 } else {
1451 return;
1452 }
1453
1454 /* set the packetizer registers */
1455 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1456 HDMI_VP_PR_CD_COLOR_DEPTH_MASK;
1457 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1458
1459 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1460 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1461
1462 /* Data from pixel repeater block */
1463 if (hdmi_data->pix_repet_factor > 0) {
1464 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1465 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1466 } else { /* data from packetizer block */
1467 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1468 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1469 }
1470
1471 hdmi_modb(hdmi, vp_conf,
1472 HDMI_VP_CONF_PR_EN_MASK |
1473 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1474
1475 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1476 HDMI_VP_STUFF);
1477
1478 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1479
1480 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1481 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1482 HDMI_VP_CONF_PP_EN_ENABLE |
1483 HDMI_VP_CONF_YCC422_EN_DISABLE;
1484 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1485 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1486 HDMI_VP_CONF_PP_EN_DISABLE |
1487 HDMI_VP_CONF_YCC422_EN_ENABLE;
1488 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1489 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1490 HDMI_VP_CONF_PP_EN_DISABLE |
1491 HDMI_VP_CONF_YCC422_EN_DISABLE;
1492 } else {
1493 return;
1494 }
1495
1496 hdmi_modb(hdmi, vp_conf,
1497 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1498 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1499
1500 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1501 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1502 HDMI_VP_STUFF_PP_STUFFING_MASK |
1503 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1504
1505 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1506 HDMI_VP_CONF);
1507 }
1508
hdmi_video_sample(struct dw_hdmi * hdmi)1509 static void hdmi_video_sample(struct dw_hdmi *hdmi)
1510 {
1511 int color_format = 0;
1512 u8 val;
1513
1514 switch (hdmi->hdmi_data.enc_in_bus_format) {
1515 case MEDIA_BUS_FMT_RGB888_1X24:
1516 color_format = 0x01;
1517 break;
1518 case MEDIA_BUS_FMT_RGB101010_1X30:
1519 color_format = 0x03;
1520 break;
1521 case MEDIA_BUS_FMT_RGB121212_1X36:
1522 color_format = 0x05;
1523 break;
1524 case MEDIA_BUS_FMT_RGB161616_1X48:
1525 color_format = 0x07;
1526 break;
1527
1528 case MEDIA_BUS_FMT_YUV8_1X24:
1529 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1530 color_format = 0x09;
1531 break;
1532 case MEDIA_BUS_FMT_YUV10_1X30:
1533 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1534 color_format = 0x0B;
1535 break;
1536 case MEDIA_BUS_FMT_YUV12_1X36:
1537 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1538 color_format = 0x0D;
1539 break;
1540 case MEDIA_BUS_FMT_YUV16_1X48:
1541 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1542 color_format = 0x0F;
1543 break;
1544
1545 case MEDIA_BUS_FMT_UYVY8_1X16:
1546 color_format = 0x16;
1547 break;
1548 case MEDIA_BUS_FMT_UYVY10_1X20:
1549 color_format = 0x14;
1550 break;
1551 case MEDIA_BUS_FMT_UYVY12_1X24:
1552 color_format = 0x12;
1553 break;
1554
1555 default:
1556 return;
1557 }
1558
1559 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
1560 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
1561 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
1562 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1563
1564 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1565 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
1566 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
1567 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
1568 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1569 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1570 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1571 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1572 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1573 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1574 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1575 }
1576
dw_hdmi_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,struct display_state * state)1577 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
1578 struct display_state *state)
1579 {
1580 if (hdmi->phy.enabled) {
1581 hdmi->phy.ops->disable(conn, hdmi, state);
1582 hdmi->phy.enabled = false;
1583 }
1584 }
1585
hdmi_config_AVI(struct dw_hdmi * hdmi,struct drm_display_mode * mode)1586 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1587 {
1588 struct hdmi_avi_infoframe frame;
1589 u8 val;
1590 bool is_hdmi2 = false;
1591 enum hdmi_quantization_range rgb_quant_range =
1592 hdmi->hdmi_data.quant_range;
1593
1594 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
1595 hdmi->edid_data.display_info.hdmi.scdc.supported)
1596 is_hdmi2 = true;
1597 /* Initialise info frame from DRM mode */
1598 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1599
1600 /*
1601 * Ignore monitor selectable quantization, use quantization set
1602 * by the user
1603 */
1604 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
1605 true, is_hdmi2);
1606 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1607 frame.colorspace = HDMI_COLORSPACE_YUV444;
1608 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1609 frame.colorspace = HDMI_COLORSPACE_YUV422;
1610 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1611 frame.colorspace = HDMI_COLORSPACE_YUV420;
1612 else
1613 frame.colorspace = HDMI_COLORSPACE_RGB;
1614
1615 /* Set up colorimetry */
1616 switch (hdmi->hdmi_data.enc_out_encoding) {
1617 case V4L2_YCBCR_ENC_601:
1618 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1619 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1620 else
1621 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1622 frame.extended_colorimetry =
1623 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1624 break;
1625 case V4L2_YCBCR_ENC_709:
1626 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1627 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1628 else
1629 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1630 frame.extended_colorimetry =
1631 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1632 break;
1633 default: /* Carries no data */
1634 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1635 frame.extended_colorimetry =
1636 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1637 break;
1638 }
1639
1640 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1641
1642 /*
1643 * The Designware IP uses a different byte format from standard
1644 * AVI info frames, though generally the bits are in the correct
1645 * bytes.
1646 */
1647
1648 /*
1649 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1650 * 5,6,7, active aspect present in bit 6 rather than 4.
1651 */
1652 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1653 if (frame.active_aspect & 15)
1654 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1655 if (frame.top_bar || frame.bottom_bar)
1656 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1657 if (frame.left_bar || frame.right_bar)
1658 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1659 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1660
1661 /* AVI data byte 2 differences: none */
1662 val = ((frame.colorimetry & 0x3) << 6) |
1663 ((frame.picture_aspect & 0x3) << 4) |
1664 (frame.active_aspect & 0xf);
1665 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1666
1667 /* AVI data byte 3 differences: none */
1668 val = ((frame.extended_colorimetry & 0x7) << 4) |
1669 ((frame.quantization_range & 0x3) << 2) |
1670 (frame.nups & 0x3);
1671 if (frame.itc)
1672 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1673 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1674
1675 /* AVI data byte 4 differences: none */
1676 val = frame.video_code & 0x7f;
1677 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1678
1679 /* AVI Data Byte 5- set up input and output pixel repetition */
1680 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1681 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1682 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1683 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1684 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1685 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1686 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1687
1688 /*
1689 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1690 * ycc range in bits 2,3 rather than 6,7
1691 */
1692 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1693 (frame.content_type & 0x3);
1694 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1695
1696 /* AVI Data Bytes 6-13 */
1697 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1698 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1699 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1700 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1701 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1702 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1703 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1704 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1705 }
1706
hdmi_config_vendor_specific_infoframe(struct dw_hdmi * hdmi,struct drm_display_mode * mode)1707 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1708 struct drm_display_mode *mode)
1709 {
1710 struct hdmi_vendor_infoframe frame;
1711 u8 buffer[10];
1712 ssize_t err;
1713
1714 /* Disable HDMI vendor specific infoframe send */
1715 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1716 HDMI_FC_DATAUTO0_VSD_MASK);
1717
1718 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1719 if (err < 0)
1720 /*
1721 * Going into that statement does not means vendor infoframe
1722 * fails. It just informed us that vendor infoframe is not
1723 * needed for the selected mode. Only 4k or stereoscopic 3D
1724 * mode requires vendor infoframe. So just simply return.
1725 */
1726 return;
1727
1728 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1729 if (err < 0) {
1730 printf("Failed to pack vendor infoframe: %zd\n", err);
1731 return;
1732 }
1733
1734 /* Set the length of HDMI vendor specific InfoFrame payload */
1735 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1736
1737 /* Set 24bit IEEE Registration Identifier */
1738 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1739 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1740 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1741
1742 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1743 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1744 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1745
1746 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1747 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1748
1749 /* Packet frame interpolation */
1750 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1751
1752 /* Auto packets per frame and line spacing */
1753 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1754
1755 /* Configures the Frame Composer On RDRB mode */
1756 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1757 HDMI_FC_DATAUTO0_VSD_MASK);
1758 }
1759
hdmi_set_cts_n(struct dw_hdmi * hdmi,unsigned int cts,unsigned int n)1760 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
1761 unsigned int n)
1762 {
1763 /* Must be set/cleared first */
1764 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
1765
1766 /* nshift factor = 0 */
1767 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
1768
1769 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
1770 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
1771 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
1772 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
1773
1774 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
1775 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
1776 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
1777 }
1778
hdmi_match_tmds_n_table(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long freq)1779 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
1780 unsigned long pixel_clk,
1781 unsigned long freq)
1782 {
1783 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
1784 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
1785 int i;
1786
1787 if (plat_data->tmds_n_table) {
1788 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
1789 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
1790 tmds_n = &plat_data->tmds_n_table[i];
1791 break;
1792 }
1793 }
1794 }
1795
1796 if (!tmds_n) {
1797 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
1798 if (pixel_clk == common_tmds_n_table[i].tmds) {
1799 tmds_n = &common_tmds_n_table[i];
1800 break;
1801 }
1802 }
1803 }
1804
1805 if (!tmds_n)
1806 return -ENOENT;
1807
1808 switch (freq) {
1809 case 32000:
1810 return tmds_n->n_32k;
1811 case 44100:
1812 case 88200:
1813 case 176400:
1814 return (freq / 44100) * tmds_n->n_44k1;
1815 case 48000:
1816 case 96000:
1817 case 192000:
1818 return (freq / 48000) * tmds_n->n_48k;
1819 default:
1820 return -ENOENT;
1821 }
1822 }
1823
hdmi_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)1824 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
1825 unsigned int pixel_clk)
1826 {
1827 u64 final, diff;
1828 u64 cts;
1829
1830 final = (u64)pixel_clk * n;
1831
1832 cts = final;
1833 do_div(cts, 128 * freq);
1834
1835 diff = final - (u64)cts * (128 * freq);
1836
1837 return diff;
1838 }
1839
hdmi_compute_n(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long freq)1840 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
1841 unsigned long pixel_clk,
1842 unsigned long freq)
1843 {
1844 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
1845 unsigned int max_n = (128 * freq) / 300;
1846 unsigned int ideal_n = (128 * freq) / 1000;
1847 unsigned int best_n_distance = ideal_n;
1848 unsigned int best_n = 0;
1849 u64 best_diff = U64_MAX;
1850 int n;
1851
1852 /* If the ideal N could satisfy the audio math, then just take it */
1853 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
1854 return ideal_n;
1855
1856 for (n = min_n; n <= max_n; n++) {
1857 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
1858
1859 if (diff < best_diff || (diff == best_diff &&
1860 abs(n - ideal_n) < best_n_distance)) {
1861 best_n = n;
1862 best_diff = diff;
1863 best_n_distance = abs(best_n - ideal_n);
1864 }
1865
1866 /*
1867 * The best N already satisfy the audio math, and also be
1868 * the closest value to ideal N, so just cut the loop.
1869 */
1870 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
1871 break;
1872 }
1873
1874 return best_n;
1875 }
1876
hdmi_find_n(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long sample_rate)1877 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
1878 unsigned long sample_rate)
1879 {
1880 int n;
1881
1882 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
1883 if (n > 0)
1884 return n;
1885
1886 printf("Rate %lu missing; compute N dynamically\n",
1887 pixel_clk);
1888
1889 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
1890 }
1891
1892 static
hdmi_set_clk_regenerator(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned int sample_rate)1893 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk,
1894 unsigned int sample_rate)
1895 {
1896 unsigned long ftdms = pixel_clk;
1897 unsigned int n, cts;
1898 u64 tmp;
1899
1900 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
1901
1902 /*
1903 * Compute the CTS value from the N value. Note that CTS and N
1904 * can be up to 20 bits in total, so we need 64-bit math. Also
1905 * note that our TDMS clock is not fully accurate; it is accurate
1906 * to kHz. This can introduce an unnecessary remainder in the
1907 * calculation below, so we don't try to warn about that.
1908 */
1909 tmp = (u64)ftdms * n;
1910 do_div(tmp, 128 * sample_rate);
1911 cts = tmp;
1912
1913 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__,
1914 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts);
1915
1916 hdmi->audio_n = n;
1917 hdmi->audio_cts = cts;
1918 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
1919 }
1920
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi * hdmi)1921 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
1922 {
1923 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
1924 hdmi->sample_rate);
1925 }
1926
hdmi_enable_audio_clk(struct dw_hdmi * hdmi)1927 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1928 {
1929 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1930 }
1931
dw_hdmi_set_sample_rate(struct dw_hdmi * hdmi,unsigned int rate)1932 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
1933 {
1934 hdmi->sample_rate = rate;
1935 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
1936 hdmi->sample_rate);
1937 }
1938
1939 #ifndef CONFIG_SPL_BUILD
dw_hdmi_hdcp_load_key(struct dw_hdmi * hdmi)1940 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi)
1941 {
1942 int i, j, ret, val;
1943 struct hdcp_keys *hdcp_keys;
1944
1945 val = sizeof(*hdcp_keys);
1946 hdcp_keys = malloc(val);
1947 if (!hdcp_keys)
1948 return -ENOMEM;
1949
1950 memset(hdcp_keys, 0, val);
1951
1952 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val);
1953 if (ret < val) {
1954 printf("HDCP: read size %d\n", ret);
1955 free(hdcp_keys);
1956 return -EINVAL;
1957 }
1958
1959 if (hdcp_keys->KSV[0] == 0x00 &&
1960 hdcp_keys->KSV[1] == 0x00 &&
1961 hdcp_keys->KSV[2] == 0x00 &&
1962 hdcp_keys->KSV[3] == 0x00 &&
1963 hdcp_keys->KSV[4] == 0x00) {
1964 printf("HDCP: Invalid hdcp key\n");
1965 free(hdcp_keys);
1966 return -EINVAL;
1967 }
1968
1969 /* Disable decryption logic */
1970 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL);
1971 /* Poll untile DPK write is allowed */
1972 do {
1973 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1974 } while ((val & DPK_WR_OK_STS) == 0);
1975
1976 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6);
1977 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5);
1978
1979 /* The useful data in ksv should be 5 byte */
1980 for (i = 4; i >= 0; i--)
1981 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i);
1982 /* Poll untile DPK write is allowed */
1983 do {
1984 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1985 } while ((val & DPK_WR_OK_STS) == 0);
1986
1987 /* Enable decryption logic */
1988 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL);
1989 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1);
1990 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0);
1991
1992 /* Write encrypt device private key */
1993 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) {
1994 for (j = 6; j >= 0; j--)
1995 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j],
1996 HDMI_HDCPREG_DPK0 + j);
1997 do {
1998 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1999 } while ((val & DPK_WR_OK_STS) == 0);
2000 }
2001
2002 free(hdcp_keys);
2003 return 0;
2004 }
2005 #endif
2006
hdmi_tx_hdcp_config(struct dw_hdmi * hdmi,const struct drm_display_mode * mode)2007 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi,
2008 const struct drm_display_mode *mode)
2009 {
2010 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi;
2011
2012 if (!hdmi->hdcp1x_enable)
2013 return;
2014
2015 /* Configure the video polarity */
2016 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ?
2017 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH :
2018 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW;
2019 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ?
2020 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH :
2021 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW;
2022 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
2023 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol,
2024 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK |
2025 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK |
2026 HDMI_A_VIDPOLCFG_DATAENPOL_MASK,
2027 HDMI_A_VIDPOLCFG);
2028
2029 /* Config the display mode */
2030 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI :
2031 HDMI_A_HDCPCFG0_HDMIDVI_DVI;
2032 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2033 HDMI_A_HDCPCFG0);
2034
2035 #ifndef CONFIG_SPL_BUILD
2036 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f))
2037 dw_hdmi_hdcp_load_key(hdmi);
2038 #endif
2039
2040 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE,
2041 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK,
2042 HDMI_FC_INVIDCONF);
2043
2044 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) {
2045 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE |
2046 HDMI_HDCP2_FORCE_DISABLE,
2047 HDMI_HDCP2_OVR_EN_MASK |
2048 HDMI_HDCP2_FORCE_MASK,
2049 HDMI_HDCP2REG_CTRL);
2050 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK);
2051 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE);
2052 }
2053
2054 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG);
2055 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE |
2056 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE |
2057 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE,
2058 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK |
2059 HDMI_A_HDCPCFG0_EN11FEATURE_MASK |
2060 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0);
2061
2062 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE |
2063 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE,
2064 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK |
2065 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1);
2066
2067 /* Reset HDCP Engine */
2068 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) {
2069 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT,
2070 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1);
2071 }
2072
2073 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK);
2074 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE,
2075 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
2076
2077 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE,
2078 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS);
2079
2080 printf("%s success\n", __func__);
2081 }
2082
dw_hdmi_setup(struct dw_hdmi * hdmi,struct rockchip_connector * conn,struct drm_display_mode * mode,struct display_state * state)2083 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2084 struct rockchip_connector *conn,
2085 struct drm_display_mode *mode,
2086 struct display_state *state)
2087 {
2088 int ret;
2089 void *data = hdmi->plat_data->phy_data;
2090
2091 hdmi_disable_overflow_interrupts(hdmi);
2092 if (!hdmi->vic)
2093 printf("Non-CEA mode used in HDMI\n");
2094 else
2095 printf("CEA mode used vic=%d\n", hdmi->vic);
2096
2097 if (hdmi->plat_data->get_enc_out_encoding)
2098 hdmi->hdmi_data.enc_out_encoding =
2099 hdmi->plat_data->get_enc_out_encoding(data);
2100 else if (hdmi->vic == 6 || hdmi->vic == 7 ||
2101 hdmi->vic == 21 || hdmi->vic == 22 ||
2102 hdmi->vic == 2 || hdmi->vic == 3 ||
2103 hdmi->vic == 17 || hdmi->vic == 18)
2104 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2105 else
2106 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2107
2108 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2109 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
2110 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
2111 } else {
2112 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2113 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2114 }
2115
2116 /* TOFIX: Get input encoding from plat data or fallback to none */
2117 if (hdmi->plat_data->get_enc_in_encoding)
2118 hdmi->hdmi_data.enc_in_encoding =
2119 hdmi->plat_data->get_enc_in_encoding(data);
2120 else if (hdmi->plat_data->input_bus_encoding)
2121 hdmi->hdmi_data.enc_in_encoding =
2122 hdmi->plat_data->input_bus_encoding;
2123 else
2124 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2125
2126 if (hdmi->plat_data->get_quant_range)
2127 hdmi->hdmi_data.quant_range =
2128 hdmi->plat_data->get_quant_range(data);
2129 else
2130 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
2131
2132 /*
2133 * According to the dw-hdmi specification 6.4.2
2134 * vp_pr_cd[3:0]:
2135 * 0000b: No pixel repetition (pixel sent only once)
2136 * 0001b: Pixel sent two times (pixel repeated once)
2137 */
2138 hdmi->hdmi_data.pix_repet_factor =
2139 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
2140 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2141
2142 /* HDMI Initialization Step B.1 */
2143 hdmi_av_composer(hdmi, mode);
2144
2145 /* HDMI Initialization Step B.2 */
2146 ret = hdmi->phy.ops->init(conn, hdmi, state);
2147 if (ret)
2148 return ret;
2149 hdmi->phy.enabled = true;
2150
2151 /* HDMI Initializateion Step B.3 */
2152 dw_hdmi_enable_video_path(hdmi);
2153
2154 /* HDMI Initialization Step E - Configure audio */
2155 if (hdmi->sink_has_audio) {
2156 printf("sink has audio support\n");
2157 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2158 hdmi_enable_audio_clk(hdmi);
2159 }
2160
2161 /* not for DVI mode */
2162 if (hdmi->sink_is_hdmi) {
2163 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2164 hdmi_config_AVI(hdmi, mode);
2165 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2166 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI,
2167 HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2168 HDMI_A_HDCPCFG0);
2169 } else {
2170 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI,
2171 HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2172 HDMI_A_HDCPCFG0);
2173 printf("%s DVI mode\n", __func__);
2174 }
2175
2176 hdmi_video_packetize(hdmi);
2177 hdmi_video_csc(hdmi);
2178 hdmi_video_sample(hdmi);
2179 hdmi_tx_hdcp_config(hdmi, mode);
2180 dw_hdmi_clear_overflow(hdmi);
2181
2182 return 0;
2183 }
2184
dw_hdmi_detect_hotplug(struct dw_hdmi * hdmi,struct display_state * state)2185 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi,
2186 struct display_state *state)
2187 {
2188 struct connector_state *conn_state = &state->conn_state;
2189 struct rockchip_connector *conn = conn_state->connector;
2190 int ret;
2191
2192 ret = hdmi->phy.ops->read_hpd(hdmi, state);
2193 if (!ret) {
2194 if (conn->bridge)
2195 ret = rockchip_bridge_detect(conn->bridge);
2196 }
2197
2198 return ret;
2199 }
2200
dw_hdmi_set_reg_wr(struct dw_hdmi * hdmi)2201 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi)
2202 {
2203 switch (hdmi->io_width) {
2204 case 4:
2205 hdmi->write = dw_hdmi_writel;
2206 hdmi->read = dw_hdmi_readl;
2207 break;
2208 case 1:
2209 hdmi->write = dw_hdmi_writeb;
2210 hdmi->read = dw_hdmi_readb;
2211 break;
2212 default:
2213 printf("reg-io-width must be 1 or 4\n");
2214 return -EINVAL;
2215 }
2216
2217 return 0;
2218 }
2219
initialize_hdmi_mutes(struct dw_hdmi * hdmi)2220 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi)
2221 {
2222 /*mute unnecessary interrupt, only enable hpd */
2223 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2224 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2225 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2226 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2227 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2228 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2229 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2230 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0);
2231 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2232 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2233 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2234 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2235 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2236 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0);
2237
2238 /*Force output black*/
2239 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2);
2240 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1);
2241 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0);
2242 }
2243
dw_hdmi_dev_init(struct dw_hdmi * hdmi)2244 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi)
2245 {
2246 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2247 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2248
2249 initialize_hdmi_mutes(hdmi);
2250 }
2251
dw_hdmi_i2c_set_divs(struct dw_hdmi * hdmi)2252 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
2253 {
2254 unsigned long low_ns, high_ns;
2255 unsigned long div_low, div_high;
2256
2257 /* Standard-mode */
2258 if (hdmi->i2c->scl_high_ns < 4000)
2259 high_ns = 4708;
2260 else
2261 high_ns = hdmi->i2c->scl_high_ns;
2262
2263 if (hdmi->i2c->scl_low_ns < 4700)
2264 low_ns = 4916;
2265 else
2266 low_ns = hdmi->i2c->scl_low_ns;
2267
2268 div_low = (24000 * low_ns) / 1000000;
2269 if ((24000 * low_ns) % 1000000)
2270 div_low++;
2271
2272 div_high = (24000 * high_ns) / 1000000;
2273 if ((24000 * high_ns) % 1000000)
2274 div_high++;
2275
2276 /* Maximum divider supported by hw is 0xffff */
2277 if (div_low > 0xffff)
2278 div_low = 0xffff;
2279
2280 if (div_high > 0xffff)
2281 div_high = 0xffff;
2282
2283 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
2284 hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
2285 HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
2286 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
2287 hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
2288 HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
2289 }
2290
dw_hdmi_i2c_init(struct dw_hdmi * hdmi)2291 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
2292 {
2293 /* Software reset */
2294 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
2295
2296 /* Set Standard Mode speed */
2297 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
2298 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
2299
2300 /* Set done, not acknowledged and arbitration interrupt polarities */
2301 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
2302 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
2303 HDMI_I2CM_CTLINT);
2304
2305 /* Clear DONE and ERROR interrupts */
2306 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
2307 HDMI_IH_I2CM_STAT0);
2308
2309 /* Mute DONE and ERROR interrupts */
2310 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
2311 HDMI_IH_MUTE_I2CM_STAT0);
2312
2313 /* set SDA high level holding time */
2314 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
2315
2316 dw_hdmi_i2c_set_divs(hdmi);
2317 }
2318
dw_hdmi_audio_enable(struct dw_hdmi * hdmi)2319 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
2320 {
2321 hdmi->audio_enable = true;
2322 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
2323 }
2324
dw_hdmi_audio_disable(struct dw_hdmi * hdmi)2325 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
2326 {
2327 hdmi->audio_enable = false;
2328 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
2329 }
2330
rockchip_dw_hdmi_init(struct rockchip_connector * conn,struct display_state * state)2331 int rockchip_dw_hdmi_init(struct rockchip_connector *conn, struct display_state *state)
2332 {
2333 struct connector_state *conn_state = &state->conn_state;
2334 const struct dw_hdmi_plat_data *pdata =
2335 #ifdef CONFIG_SPL_BUILD
2336 (const struct dw_hdmi_plat_data *)conn->data;
2337 #else
2338 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev);
2339 ofnode hdmi_node = conn->dev->node;
2340 struct device_node *ddc_node;
2341 int ret;
2342 #endif
2343 struct crtc_state *crtc_state = &state->crtc_state;
2344 struct dw_hdmi *hdmi;
2345 struct drm_display_mode *mode_buf;
2346 u32 val;
2347
2348 hdmi = malloc(sizeof(struct dw_hdmi));
2349 if (!hdmi)
2350 return -ENOMEM;
2351
2352 memset(hdmi, 0, sizeof(struct dw_hdmi));
2353 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode));
2354 if (!mode_buf)
2355 return -ENOMEM;
2356
2357 #ifdef CONFIG_SPL_BUILD
2358 hdmi->id = 0;
2359 hdmi->regs = (void *)RK3528_HDMI_BASE;
2360 hdmi->io_width = 4;
2361 hdmi->scramble_low_rates = false;
2362 hdmi->hdcp1x_enable = false;
2363 hdmi->output_bus_format_rgb = false;
2364 conn_state->type = DRM_MODE_CONNECTOR_HDMIA;
2365 #else
2366 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi");
2367 if (hdmi->id < 0)
2368 hdmi->id = 0;
2369 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2370 #endif
2371
2372 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode));
2373
2374 hdmi->dev_type = pdata->dev_type;
2375 hdmi->plat_data = pdata;
2376
2377 #ifndef CONFIG_SPL_BUILD
2378 hdmi->regs = dev_read_addr_ptr(conn->dev);
2379 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1);
2380
2381 if (ofnode_read_bool(hdmi_node, "scramble-low-rates"))
2382 hdmi->scramble_low_rates = true;
2383
2384 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable"))
2385 hdmi->hdcp1x_enable = true;
2386 else
2387 hdmi->hdcp1x_enable = false;
2388
2389 if (ofnode_read_bool(hdmi_node, "force_output_bus_format_RGB") ||
2390 ofnode_read_bool(hdmi_node, "unsupported-yuv-input"))
2391 hdmi->output_bus_format_rgb = true;
2392 else
2393 hdmi->output_bus_format_rgb = false;
2394
2395 ret = dev_read_size(conn->dev, "rockchip,phy-table");
2396 if (ret > 0 && hdmi->plat_data->phy_config) {
2397 u32 phy_config[ret / 4];
2398 int i;
2399
2400 dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4);
2401
2402 for (i = 0; i < ret / 16; i++) {
2403 if (phy_config[i * 4] != 0)
2404 hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4];
2405 else
2406 hdmi->plat_data->phy_config[i].mpixelclock = ~0UL;
2407 hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1];
2408 hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2];
2409 hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3];
2410 }
2411 }
2412
2413 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0);
2414 if (ddc_node) {
2415 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node),
2416 &hdmi->adap.i2c_bus);
2417 if (hdmi->adap.i2c_bus)
2418 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus);
2419 }
2420 #endif
2421
2422 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
2423 if (hdmi->grf <= 0) {
2424 printf("%s: Get syscon grf failed (ret=%p)\n",
2425 __func__, hdmi->grf);
2426 return -ENXIO;
2427 }
2428
2429 #ifdef CONFIG_SPL_BUILD
2430 hdmi->gpio_base = (void *)RK3528_GPIO_BASE;
2431 #else
2432 ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0,
2433 &hdmi->hpd_gpiod, GPIOD_IS_IN);
2434 if (ret && ret != -ENOENT) {
2435 printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret);
2436 return ret;
2437 }
2438 hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1);
2439 #endif
2440 if (!hdmi->gpio_base)
2441 return -ENODEV;
2442
2443 dw_hdmi_set_reg_wr(hdmi);
2444
2445 if (pdata->grf_vop_sel_reg) {
2446 if (crtc_state->crtc_id)
2447 val = ((1 << pdata->vop_sel_bit) |
2448 (1 << (16 + pdata->vop_sel_bit)));
2449 else
2450 val = ((0 << pdata->vop_sel_bit) |
2451 (1 << (16 + pdata->vop_sel_bit)));
2452 writel(val, hdmi->grf + pdata->grf_vop_sel_reg);
2453 }
2454
2455 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c));
2456 if (!hdmi->i2c)
2457 return -ENOMEM;
2458 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer;
2459
2460 /*
2461 * Read high and low time from device tree. If not available use
2462 * the default timing scl clock rate is about 99.6KHz.
2463 */
2464 #ifdef CONFIG_SPL_BUILD
2465 hdmi->i2c->scl_high_ns = 9625;
2466 hdmi->i2c->scl_low_ns = 10000;
2467 #else
2468 hdmi->i2c->scl_high_ns =
2469 ofnode_read_s32_default(hdmi_node,
2470 "ddc-i2c-scl-high-time-ns", 4708);
2471 hdmi->i2c->scl_low_ns =
2472 ofnode_read_s32_default(hdmi_node,
2473 "ddc-i2c-scl-low-time-ns", 4916);
2474 #endif
2475
2476 dw_hdmi_i2c_init(hdmi);
2477 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0;
2478 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
2479
2480 hdmi->edid_data.mode_buf = mode_buf;
2481 hdmi->sample_rate = 48000;
2482
2483 conn->data = hdmi;
2484 dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base,
2485 &hdmi->hpd_gpiod, hdmi->dev_type);
2486 dw_hdmi_detect_phy(hdmi);
2487 dw_hdmi_dev_init(hdmi);
2488
2489 return 0;
2490 }
2491
rockchip_dw_hdmi_deinit(struct rockchip_connector * conn,struct display_state * state)2492 void rockchip_dw_hdmi_deinit(struct rockchip_connector *conn, struct display_state *state)
2493 {
2494 struct dw_hdmi *hdmi = conn->data;
2495
2496 if (hdmi->i2c)
2497 free(hdmi->i2c);
2498 if (hdmi->edid_data.mode_buf)
2499 free(hdmi->edid_data.mode_buf);
2500 if (hdmi)
2501 free(hdmi);
2502 }
2503
rockchip_dw_hdmi_config_output(struct rockchip_connector * conn,struct display_state * state)2504 static void rockchip_dw_hdmi_config_output(struct rockchip_connector *conn,
2505 struct display_state *state)
2506 {
2507 struct connector_state *conn_state = &state->conn_state;
2508 struct drm_display_mode *mode = &conn_state->mode;
2509 struct dw_hdmi *hdmi = conn->data;
2510 unsigned int bus_format;
2511 unsigned long enc_out_encoding;
2512 struct overscan *overscan = &conn_state->overscan;
2513
2514 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format,
2515 overscan, hdmi->dev_type, hdmi->output_bus_format_rgb);
2516
2517 *mode = *hdmi->edid_data.preferred_mode;
2518 hdmi->vic = drm_match_cea_mode(mode);
2519
2520 if (state->force_output) {
2521 hdmi->force_output = state->force_output;
2522 hdmi->sink_is_hdmi = true;
2523 hdmi->sink_has_audio = true;
2524 bus_format = state->force_bus_format;
2525 }
2526 conn_state->bus_format = bus_format;
2527 hdmi->hdmi_data.enc_in_bus_format = bus_format;
2528 hdmi->hdmi_data.enc_out_bus_format = bus_format;
2529
2530 switch (bus_format) {
2531 case MEDIA_BUS_FMT_UYVY10_1X20:
2532 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30;
2533 hdmi->hdmi_data.enc_in_bus_format =
2534 MEDIA_BUS_FMT_YUV10_1X30;
2535 break;
2536 case MEDIA_BUS_FMT_UYVY8_1X16:
2537 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
2538 hdmi->hdmi_data.enc_in_bus_format =
2539 MEDIA_BUS_FMT_YUV8_1X24;
2540 break;
2541 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2542 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2543 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420;
2544 break;
2545 }
2546
2547 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 ||
2548 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 ||
2549 hdmi->vic == 17 || hdmi->vic == 18)
2550 enc_out_encoding = V4L2_YCBCR_ENC_601;
2551 else
2552 enc_out_encoding = V4L2_YCBCR_ENC_709;
2553
2554 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020)
2555 conn_state->color_encoding = DRM_COLOR_YCBCR_BT2020;
2556 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 ||
2557 bus_format == MEDIA_BUS_FMT_RGB101010_1X30)
2558 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709;
2559 else if (enc_out_encoding == V4L2_YCBCR_ENC_709)
2560 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709;
2561 else
2562 conn_state->color_encoding = DRM_COLOR_YCBCR_BT601;
2563
2564 if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 ||
2565 bus_format == MEDIA_BUS_FMT_RGB101010_1X30)
2566 conn_state->color_range = hdmi->hdmi_data.quant_range ==
2567 HDMI_QUANTIZATION_RANGE_LIMITED ?
2568 DRM_COLOR_YCBCR_LIMITED_RANGE :
2569 DRM_COLOR_YCBCR_FULL_RANGE;
2570 else
2571 conn_state->color_range = hdmi->hdmi_data.quant_range ==
2572 HDMI_QUANTIZATION_RANGE_FULL ?
2573 DRM_COLOR_YCBCR_FULL_RANGE :
2574 DRM_COLOR_YCBCR_LIMITED_RANGE;
2575 }
2576
rockchip_dw_hdmi_prepare(struct rockchip_connector * conn,struct display_state * state)2577 int rockchip_dw_hdmi_prepare(struct rockchip_connector *conn, struct display_state *state)
2578 {
2579 struct connector_state *conn_state = &state->conn_state;
2580 struct drm_display_mode *mode = &conn_state->mode;
2581 struct dw_hdmi *hdmi = conn->data;
2582
2583 if (!hdmi->edid_data.preferred_mode && conn->bridge) {
2584 drm_add_hdmi_modes(&hdmi->edid_data, mode);
2585 drm_mode_sort(&hdmi->edid_data);
2586 hdmi->sink_is_hdmi = true;
2587 hdmi->sink_has_audio = true;
2588 rockchip_dw_hdmi_config_output(conn, state);
2589 }
2590
2591 return 0;
2592 }
2593
rockchip_dw_hdmi_enable(struct rockchip_connector * conn,struct display_state * state)2594 int rockchip_dw_hdmi_enable(struct rockchip_connector *conn, struct display_state *state)
2595 {
2596 struct connector_state *conn_state = &state->conn_state;
2597 struct drm_display_mode *mode = &conn_state->mode;
2598 struct dw_hdmi *hdmi = conn->data;
2599
2600 if (!hdmi)
2601 return -EFAULT;
2602
2603 /* Store the display mode for plugin/DKMS poweron events */
2604 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2605
2606 dw_hdmi_setup(hdmi, conn, mode, state);
2607
2608 return 0;
2609 }
2610
rockchip_dw_hdmi_disable(struct rockchip_connector * conn,struct display_state * state)2611 int rockchip_dw_hdmi_disable(struct rockchip_connector *conn, struct display_state *state)
2612 {
2613 struct dw_hdmi *hdmi = conn->data;
2614
2615 dw_hdmi_disable(conn, hdmi, state);
2616 return 0;
2617 }
2618
rockchip_dw_hdmi_mode_valid(struct dw_hdmi * hdmi)2619 static void rockchip_dw_hdmi_mode_valid(struct dw_hdmi *hdmi)
2620 {
2621 struct hdmi_edid_data *edid_data = &hdmi->edid_data;
2622 int i;
2623
2624 for (i = 0; i < edid_data->modes; i++) {
2625 if (edid_data->mode_buf[i].invalid)
2626 continue;
2627
2628 if (edid_data->mode_buf[i].clock > 600000)
2629 edid_data->mode_buf[i].invalid = true;
2630 }
2631 }
2632
rockchip_dw_hdmi_get_timing(struct rockchip_connector * conn,struct display_state * state)2633 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state)
2634 {
2635 int ret = 0, i, vic;
2636 struct connector_state *conn_state = &state->conn_state;
2637 struct dw_hdmi *hdmi = conn->data;
2638 struct edid *edid = (struct edid *)conn_state->edid;
2639 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19};
2640
2641 if (!hdmi)
2642 return -EFAULT;
2643
2644 conn_state->edid = drm_do_get_edid(&hdmi->adap);
2645
2646 if (conn_state->edid) {
2647 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2648 if (hdmi->sink_has_audio)
2649 hdmi->sink_is_hdmi = true;
2650 else
2651 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2652
2653 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
2654 }
2655 if (ret <= 0) {
2656 hdmi->sink_is_hdmi = true;
2657 hdmi->sink_has_audio = true;
2658 do_cea_modes(&hdmi->edid_data, def_modes_vic,
2659 sizeof(def_modes_vic));
2660 hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED;
2661 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0];
2662 printf("failed to get edid\n");
2663 }
2664 #ifdef CONFIG_SPL_BUILD
2665 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2666 #endif
2667 drm_rk_filter_whitelist(&hdmi->edid_data);
2668 rockchip_dw_hdmi_mode_valid(hdmi);
2669 if (hdmi->phy.ops->mode_valid)
2670 hdmi->phy.ops->mode_valid(conn, hdmi, state);
2671 drm_mode_max_resolution_filter(&hdmi->edid_data,
2672 &state->crtc_state.max_output);
2673 if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
2674 printf("can't find valid hdmi mode\n");
2675 return -EINVAL;
2676 }
2677
2678 for (i = 0; i < hdmi->edid_data.modes; i++) {
2679 hdmi->edid_data.mode_buf[i].vrefresh =
2680 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]);
2681
2682 vic = drm_match_cea_mode(&hdmi->edid_data.mode_buf[i]);
2683 if (hdmi->edid_data.mode_buf[i].picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
2684 if (vic >= 93 && vic <= 95)
2685 hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2686 HDMI_PICTURE_ASPECT_16_9;
2687 else if (vic == 98)
2688 hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2689 HDMI_PICTURE_ASPECT_256_135;
2690 }
2691 }
2692
2693 drm_mode_sort(&hdmi->edid_data);
2694 rockchip_dw_hdmi_config_output(conn, state);
2695
2696 return 0;
2697 }
2698
rockchip_dw_hdmi_detect(struct rockchip_connector * conn,struct display_state * state)2699 int rockchip_dw_hdmi_detect(struct rockchip_connector *conn, struct display_state *state)
2700 {
2701 int ret;
2702 struct dw_hdmi *hdmi = conn->data;
2703
2704 if (!hdmi)
2705 return -EFAULT;
2706
2707 ret = dw_hdmi_detect_hotplug(hdmi, state);
2708
2709 return ret;
2710 }
2711
rockchip_dw_hdmi_get_edid(struct rockchip_connector * conn,struct display_state * state)2712 int rockchip_dw_hdmi_get_edid(struct rockchip_connector *conn, struct display_state *state)
2713 {
2714 int ret = 0;
2715 struct connector_state *conn_state = &state->conn_state;
2716 struct dw_hdmi *hdmi = conn->data;
2717
2718 conn_state->edid = drm_do_get_edid(&hdmi->adap);
2719 if (!conn_state->edid)
2720 ret = -EINVAL;
2721
2722 return ret;
2723 }
2724
inno_dw_hdmi_phy_init(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2725 int inno_dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2726 {
2727 struct display_state *state = (struct display_state *)data;
2728 struct connector_state *conn_state = &state->conn_state;
2729 u32 color_depth, bus_width;
2730
2731 color_depth =
2732 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
2733
2734 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2735 bus_width = color_depth / 2;
2736 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
2737 bus_width = color_depth;
2738 else
2739 bus_width = 8;
2740 rockchip_phy_set_bus_width(conn->phy, bus_width);
2741 rockchip_phy_set_pll(conn->phy,
2742 conn_state->mode.crtc_clock * 1000);
2743 if (hdmi->edid_data.display_info.hdmi.scdc.supported)
2744 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi);
2745 rockchip_phy_power_on(conn->phy);
2746
2747 return 0;
2748 }
2749
inno_dw_hdmi_phy_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2750 void inno_dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2751 {
2752 }
2753
2754 enum drm_connector_status
inno_dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)2755 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)
2756 {
2757 enum drm_connector_status status;
2758 struct display_state *state = (struct display_state *)data;
2759
2760 status = dw_hdmi_phy_read_hpd(hdmi, state);
2761
2762 if (hdmi->dev_type == RK3328_HDMI) {
2763 if (status == connector_status_connected)
2764 inno_dw_hdmi_set_domain(hdmi->grf, 1);
2765 else
2766 inno_dw_hdmi_set_domain(hdmi->grf, 0);
2767 }
2768
2769 return status;
2770 }
2771
inno_dw_hdmi_mode_valid(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2772 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2773 {
2774 struct hdmi_edid_data *edid_data = &hdmi->edid_data;
2775 unsigned long rate;
2776 int i, ret;
2777 struct drm_display_mode *mode_buf = edid_data->mode_buf;
2778
2779 for (i = 0; i < edid_data->modes; i++) {
2780 if (edid_data->mode_buf[i].invalid)
2781 continue;
2782 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK)
2783 rate = mode_buf[i].clock * 1000 * 2;
2784 else
2785 rate = mode_buf[i].clock * 1000;
2786
2787 /* Check whether mode is out of phy cfg range. */
2788 ret = rockchip_phy_round_rate(conn->phy, rate);
2789
2790 if (ret < 0)
2791 edid_data->mode_buf[i].invalid = true;
2792 }
2793 }
2794