1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3506-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 compatible = "rockchip,rk3506"; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 ethernet0 = &gmac0; 23 ethernet1 = &gmac1; 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 spi2 = &fspi; 41 spi3 = &flexbus_fspi; 42 }; 43 44 clocks { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges; 49 50 clk_rc: clk-rc { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <400000>; 54 clock-output-names = "clk_rc"; 55 }; 56 57 xin24m: xin24m { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <24000000>; 61 clock-output-names = "xin24m"; 62 }; 63 64 xin32k: xin32k { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <32768>; 68 clock-output-names = "xin32k"; 69 }; 70 71 mclkin_sai0: mclkin-sai0 { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <0>; 75 clock-output-names = "sai0_mclk_in"; 76 }; 77 78 mclkin_sai1: mclkin-sai1 { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <0>; 82 clock-output-names = "sai1_mclk_in"; 83 }; 84 85 mclkin_sai2: mclkin-sai2 { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <0>; 89 clock-output-names = "sai2_mclk_in"; 90 }; 91 92 mclkin_sai3: mclkin-sai3 { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <0>; 96 clock-output-names = "sai3_mclk_in"; 97 }; 98 99 mclkout_sai0: mclkout-sai0@ff910004 { 100 compatible = "rockchip,clk-out"; 101 reg = <0xff910004 0x4>; 102 clocks = <&cru MCLK_OUT_SAI0>; 103 #clock-cells = <0>; 104 clock-output-names = "mclk_sai0_to_io"; 105 rockchip,bit-shift = <8>; 106 }; 107 108 mclkout_sai1: mclkout-sai1@ff910004 { 109 compatible = "rockchip,clk-out"; 110 reg = <0xff910004 0x4>; 111 clocks = <&cru MCLK_OUT_SAI1>; 112 #clock-cells = <0>; 113 clock-output-names = "mclk_sai1_to_io"; 114 rockchip,bit-shift = <9>; 115 }; 116 117 mclkout_sai2: mclkout-sai2@ff288004 { 118 compatible = "rockchip,clk-out"; 119 reg = <0xff288004 0x4>; 120 clocks = <&cru MCLK_OUT_SAI2>; 121 #clock-cells = <0>; 122 clock-output-names = "mclk_sai2_to_io"; 123 rockchip,bit-shift = <2>; 124 }; 125 126 mclkout_sai3: mclkout-sai3@ff288004 { 127 compatible = "rockchip,clk-out"; 128 reg = <0xff288004 0x4>; 129 clocks = <&cru MCLK_OUT_SAI3>; 130 #clock-cells = <0>; 131 clock-output-names = "mclk_sai3_to_io"; 132 rockchip,bit-shift = <3>; 133 }; 134 135 pvtpll_core: pvtpll-core@ff840000 { 136 compatible = "rockchip,rk3506-core-pvtpll", "syscon"; 137 reg = <0xff840000 0x100>; 138 #clock-cells = <0>; 139 clock-output-names = "clk_core_pvtpll"; 140 assigned-clocks = <&pvtpll_core>; 141 assigned-clock-rates = <1200000000>; 142 }; 143 }; 144 145 cpus { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 cpu0: cpu@f00 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a7"; 152 reg = <0xf00>; 153 enable-method = "psci"; 154 clocks = <&cru ARMCLK>; 155 operating-points-v2 = <&cpu0_opp_table>; 156 }; 157 158 cpu1: cpu@f01 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a7"; 161 reg = <0xf01>; 162 enable-method = "psci"; 163 clocks = <&cru ARMCLK>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 }; 166 167 cpu2: cpu@f02 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a7"; 170 reg = <0xf02>; 171 enable-method = "psci"; 172 clocks = <&cru ARMCLK>; 173 operating-points-v2 = <&cpu0_opp_table>; 174 }; 175 }; 176 177 cpu0_opp_table: cpu0-opp-table { 178 compatible = "operating-points-v2"; 179 opp-shared; 180 181 nvmem-cells = <&cpu_leakage>; 182 nvmem-cell-names = "leakage"; 183 184 rockchip,pvtm-voltage-sel = < 185 0 1584 0 186 1585 1619 1 187 1620 1654 2 188 1655 1689 3 189 1690 1724 4 190 1725 1759 5 191 1760 1794 6 192 1795 9999 7 193 >; 194 rockchip,pvtm-pvtpll; 195 rockchip,pvtm-offset = <0x18>; 196 rockchip,pvtm-sample-time = <500>; 197 rockchip,pvtm-freq = <1608000>; 198 rockchip,pvtm-volt = <1000000>; 199 rockchip,pvtm-ref-temp = <40>; 200 rockchip,pvtm-temp-prop = <0 0>; 201 rockchip,pvtm-thermal-zone = "soc-thermal"; 202 rockchip,grf = <&pvtpll_core>; 203 rockchip,temp-hysteresis = <5000>; 204 rockchip,low-temp = <10000>; 205 rockchip,low-temp-min-volt = <900000>; 206 207 opp-600000000 { 208 opp-hz = /bits/ 64 <600000000>; 209 opp-microvolt = <850000 850000 1000000>; 210 clock-latency-ns = <40000>; 211 opp-suspend; 212 }; 213 opp-800000000 { 214 opp-hz = /bits/ 64 <800000000>; 215 opp-microvolt = <850000 850000 1000000>; 216 clock-latency-ns = <40000>; 217 }; 218 opp-1008000000 { 219 opp-hz = /bits/ 64 <1008000000>; 220 opp-microvolt = <850000 850000 1000000>; 221 opp-microvolt-L0 = <875000 875000 1000000>; 222 clock-latency-ns = <40000>; 223 }; 224 opp-1200000000 { 225 opp-hz = /bits/ 64 <1200000000>; 226 opp-microvolt = <850000 850000 1000000>; 227 opp-microvolt-L0 = <875000 875000 1000000>; 228 clock-latency-ns = <40000>; 229 }; 230 opp-1296000000 { 231 opp-hz = /bits/ 64 <1296000000>; 232 opp-microvolt = <900000 900000 1000000>; 233 opp-microvolt-L0 = <900000 900000 1000000>; 234 opp-microvolt-L1 = <887500 887500 1000000>; 235 opp-microvolt-L2 = <875000 875000 1000000>; 236 opp-microvolt-L3 = <862500 862500 1000000>; 237 opp-microvolt-L4 = <850000 850000 1000000>; 238 opp-microvolt-L5 = <850000 850000 1000000>; 239 opp-microvolt-L6 = <850000 850000 1000000>; 240 opp-microvolt-L7 = <850000 850000 1000000>; 241 clock-latency-ns = <40000>; 242 }; 243 opp-1416000000 { 244 opp-hz = /bits/ 64 <1416000000>; 245 opp-microvolt = <937500 937500 1000000>; 246 opp-microvolt-L0 = <937500 937500 1000000>; 247 opp-microvolt-L1 = <925000 925000 1000000>; 248 opp-microvolt-L2 = <912500 912500 1000000>; 249 opp-microvolt-L3 = <900000 900000 1000000>; 250 opp-microvolt-L4 = <887500 887500 1000000>; 251 opp-microvolt-L5 = <875000 875000 1000000>; 252 opp-microvolt-L6 = <862500 862500 1000000>; 253 opp-microvolt-L7 = <850000 850000 1000000>; 254 clock-latency-ns = <40000>; 255 }; 256 opp-1512000000 { 257 opp-hz = /bits/ 64 <1512000000>; 258 opp-microvolt = <975000 975000 1000000>; 259 opp-microvolt-L0 = <975000 975000 1000000>; 260 opp-microvolt-L1 = <962500 962500 1000000>; 261 opp-microvolt-L2 = <950000 950000 1000000>; 262 opp-microvolt-L3 = <937500 937500 1000000>; 263 opp-microvolt-L4 = <925000 925000 1000000>; 264 opp-microvolt-L5 = <912500 912000 1000000>; 265 opp-microvolt-L6 = <900000 900000 1000000>; 266 opp-microvolt-L7 = <887500 887500 1000000>; 267 clock-latency-ns = <40000>; 268 }; 269 }; 270 271 arm_pmu: arm-pmu { 272 compatible = "arm,cortex-a7-pmu"; 273 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; 277 }; 278 279 cpuinfo { 280 compatible = "rockchip,cpuinfo"; 281 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 282 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 283 }; 284 285 display_subsystem: display-subsystem { 286 compatible = "rockchip,display-subsystem"; 287 ports = <&vop_out>; 288 status = "disabled"; 289 290 route { 291 route_dsi: route-dsi { 292 status = "disabled"; 293 logo,uboot = "logo.bmp"; 294 logo,kernel = "logo_kernel.bmp"; 295 logo,mode = "center"; 296 charge_logo,mode = "center"; 297 connect = <&vop_out_dsi>; 298 }; 299 300 route_rgb: route-rgb { 301 status = "disabled"; 302 logo,uboot = "logo.bmp"; 303 logo,kernel = "logo_kernel.bmp"; 304 logo,mode = "center"; 305 charge_logo,mode = "center"; 306 connect = <&vop_out_rgb>; 307 }; 308 }; 309 }; 310 311 psci: psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 }; 315 316 rockchip_system_monitor: rockchip-system-monitor { 317 compatible = "rockchip,system-monitor"; 318 319 rockchip,thermal-zone = "soc-thermal"; 320 }; 321 322 thermal_zones: thermal-zones { 323 soc_thermal: soc-thermal { 324 polling-delay-passive = <20>; /* milliseconds */ 325 polling-delay = <1000>; /* milliseconds */ 326 thermal-sensors = <&tsadc 0>; 327 trips { 328 soc_crit: soc-crit { 329 /* millicelsius */ 330 temperature = <115000>; 331 /* millicelsius */ 332 hysteresis = <2000>; 333 type = "critical"; 334 }; 335 }; 336 }; 337 }; 338 339 timer { 340 compatible = "arm,armv7-timer"; 341 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>, 342 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>, 343 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>, 344 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; 345 clock-frequency = <24000000>; 346 }; 347 348 dmac0: dma-controller@ff000000 { 349 compatible = "arm,pl330", "arm,primecell"; 350 reg = <0xff000000 0x4000>; 351 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru ACLK_DMAC0>; 354 clock-names = "apb_pclk"; 355 #dma-cells = <5>; 356 arm,pl330-periph-burst; 357 }; 358 359 dmac1: dma-controller@ff008000 { 360 compatible = "arm,pl330", "arm,primecell"; 361 reg = <0xff008000 0x4000>; 362 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru ACLK_DMAC1>; 365 clock-names = "apb_pclk"; 366 #dma-cells = <5>; 367 arm,pl330-periph-burst; 368 }; 369 370 i2c0: i2c@ff040000 { 371 compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; 372 reg = <0xff040000 0x1000>; 373 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 377 clock-names = "i2c", "pclk"; 378 status = "disabled"; 379 }; 380 381 i2c1: i2c@ff050000 { 382 compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; 383 reg = <0xff050000 0x1000>; 384 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 388 clock-names = "i2c", "pclk"; 389 status = "disabled"; 390 }; 391 392 i2c2: i2c@ff060000 { 393 compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; 394 reg = <0xff060000 0x1000>; 395 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 399 clock-names = "i2c", "pclk"; 400 status = "disabled"; 401 }; 402 403 uart0: serial@ff0a0000 { 404 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 405 reg = <0xff0a0000 0x100>; 406 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 407 reg-shift = <2>; 408 reg-io-width = <4>; 409 dmas = <&dmac0 4 0xff2880a8 0x03000100 0x0 0x0>, 410 <&dmac0 5 0xff2880a8 0x0c000400 0x0 0x0>; 411 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 412 clock-names = "baudclk", "apb_pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart0_xfer_pins>; 415 status = "disabled"; 416 }; 417 418 uart1: serial@ff0b0000 { 419 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 420 reg = <0xff0b0000 0x100>; 421 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 dmas = <&dmac0 6 0xff2880a8 0x30001000 0x0 0x0>, 425 <&dmac0 7 0xff2880a8 0xc0004000 0x0 0x0>; 426 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 427 clock-names = "baudclk", "apb_pclk"; 428 status = "disabled"; 429 }; 430 431 uart2: serial@ff0c0000 { 432 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 433 reg = <0xff0c0000 0x100>; 434 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 435 reg-shift = <2>; 436 reg-io-width = <4>; 437 dmas = <&dmac0 8 0xff2880ac 0x00030001 0x0 0x0>, 438 <&dmac0 9 0xff2880ac 0x000c0004 0x0 0x0>; 439 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 440 clock-names = "baudclk", "apb_pclk"; 441 status = "disabled"; 442 }; 443 444 uart3: serial@ff0d0000 { 445 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 446 reg = <0xff0d0000 0x100>; 447 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 448 reg-shift = <2>; 449 reg-io-width = <4>; 450 dmas = <&dmac0 10 0xff2880ac 0x00300010 0x0 0x0>, 451 <&dmac0 11 0xff2880ac 0x00c00040 0x0 0x0>; 452 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 453 clock-names = "baudclk", "apb_pclk"; 454 status = "disabled"; 455 }; 456 457 uart4: serial@ff0e0000 { 458 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 459 reg = <0xff0e0000 0x100>; 460 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 461 reg-shift = <2>; 462 reg-io-width = <4>; 463 dmas = <&dmac1 12 0x0 0x0 0x0 0x0>, <&dmac1 13 0x0 0x0 0x0 0x0>; 464 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 465 clock-names = "baudclk", "apb_pclk"; 466 status = "disabled"; 467 }; 468 469 spi0: spi@ff120000 { 470 compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; 471 reg = <0xff120000 0x1000>; 472 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 476 clock-names = "spiclk", "apb_pclk"; 477 dmas = <&dmac0 0 0xff2880a8 0x00030001 0x0 0x0>, 478 <&dmac0 1 0xff2880a8 0x000c0004 0x0 0x0>; 479 dma-names = "tx", "rx"; 480 num-cs = <2>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&spi0_csn0_pins &spi0_csn1_pins &spi0_clk_pins>; 483 status = "disabled"; 484 }; 485 486 spi1: spi@ff130000 { 487 compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; 488 reg = <0xff130000 0x1000>; 489 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 493 clock-names = "spiclk", "apb_pclk"; 494 dmas = <&dmac0 2 0xff2880a8 0x00300010 0x0 0x0>, 495 <&dmac0 3 0xff2880a8 0x00c00040 0x0 0x0>; 496 dma-names = "tx", "rx"; 497 num-cs = <2>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&spi1_csn0_pins &spi1_csn1_pins &spi1_clk_pins>; 500 status = "disabled"; 501 }; 502 503 pwm1_8ch_0: pwm@ff170000 { 504 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 505 reg = <0xff170000 0x200>; 506 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 508 clock-names = "pwm", "pclk"; 509 #pwm-cells = <3>; 510 status = "disabled"; 511 }; 512 513 pwm1_8ch_1: pwm@ff171000 { 514 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 515 reg = <0xff171000 0x200>; 516 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 518 clock-names = "pwm", "pclk"; 519 #pwm-cells = <3>; 520 status = "disabled"; 521 }; 522 523 pwm1_8ch_2: pwm@ff172000 { 524 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 525 reg = <0xff172000 0x200>; 526 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 528 clock-names = "pwm", "pclk"; 529 #pwm-cells = <3>; 530 status = "disabled"; 531 }; 532 533 pwm1_8ch_3: pwm@ff173000 { 534 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 535 reg = <0xff173000 0x200>; 536 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 538 clock-names = "pwm", "pclk"; 539 #pwm-cells = <3>; 540 status = "disabled"; 541 }; 542 543 pwm1_8ch_4: pwm@ff174000 { 544 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 545 reg = <0xff174000 0x200>; 546 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 548 clock-names = "pwm", "pclk"; 549 #pwm-cells = <3>; 550 status = "disabled"; 551 }; 552 553 pwm1_8ch_5: pwm@ff175000 { 554 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 555 reg = <0xff175000 0x200>; 556 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 558 clock-names = "pwm", "pclk"; 559 #pwm-cells = <3>; 560 status = "disabled"; 561 }; 562 563 pwm1_8ch_6: pwm@ff176000 { 564 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 565 reg = <0xff176000 0x200>; 566 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 568 clock-names = "pwm", "pclk"; 569 #pwm-cells = <3>; 570 status = "disabled"; 571 }; 572 573 pwm1_8ch_7: pwm@ff177000 { 574 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 575 reg = <0xff177000 0x200>; 576 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 578 clock-names = "pwm", "pclk"; 579 #pwm-cells = <3>; 580 status = "disabled"; 581 }; 582 583 hwlock0: hwspinlock@ff240000 { 584 compatible = "rockchip,hwspinlock"; 585 reg = <0xff240000 0x20>; 586 #hwlock-cells = <1>; 587 rockchip,hwlock-num-locks = <8>; 588 status = "disabled"; 589 }; 590 591 hwlock1: hwspinlock@ff241000 { 592 compatible = "rockchip,hwspinlock"; 593 reg = <0xff241000 0x20>; 594 #hwlock-cells = <1>; 595 rockchip,hwlock-num-locks = <8>; 596 status = "disabled"; 597 }; 598 599 hwlock2: hwspinlock@ff242000 { 600 compatible = "rockchip,hwspinlock"; 601 reg = <0xff242000 0x20>; 602 #hwlock-cells = <1>; 603 rockchip,hwlock-num-locks = <8>; 604 status = "disabled"; 605 }; 606 607 hwlock3: hwspinlock@ff243000 { 608 compatible = "rockchip,hwspinlock"; 609 reg = <0xff243000 0x20>; 610 #hwlock-cells = <1>; 611 rockchip,hwlock-num-locks = <8>; 612 status = "disabled"; 613 }; 614 615 wdt0: watchdog@ff260000 { 616 compatible = "snps,dw-wdt"; 617 reg = <0xff260000 0x100>; 618 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 619 clock-names = "tclk", "pclk"; 620 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 621 status = "disabled"; 622 }; 623 624 wdt1: watchdog@ff268000 { 625 compatible = "snps,dw-wdt"; 626 reg = <0xff268000 0x100>; 627 clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>; 628 clock-names = "tclk", "pclk"; 629 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 630 status = "disabled"; 631 }; 632 633 grf: syscon@ff288000 { 634 compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; 635 reg = <0xff288000 0x4000>; 636 637 rgb: rgb { 638 compatible = "rockchip,rk3506-rgb"; 639 status = "disabled"; 640 641 ports { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 port@0 { 646 reg = <0>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 rgb_in_vop: endpoint@0 { 651 reg = <0>; 652 remote-endpoint = <&vop_out_rgb>; 653 }; 654 }; 655 }; 656 }; 657 }; 658 659 mailbox0: mailbox@ff290000 { 660 compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; 661 reg = <0xff290000 0x20>; 662 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cru PCLK_MAILBOX>; 664 clock-names = "pclk_mailbox"; 665 #mbox-cells = <1>; 666 status = "disabled"; 667 }; 668 669 mailbox1: mailbox@ff291000 { 670 compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; 671 reg = <0xff291000 0x20>; 672 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru PCLK_MAILBOX>; 674 clock-names = "pclk_mailbox"; 675 #mbox-cells = <1>; 676 status = "disabled"; 677 }; 678 679 mailbox2: mailbox@ff292000 { 680 compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; 681 reg = <0xff292000 0x20>; 682 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru PCLK_MAILBOX>; 684 clock-names = "pclk_mailbox"; 685 #mbox-cells = <1>; 686 status = "disabled"; 687 }; 688 689 mailbox3: mailbox@ff293000 { 690 compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; 691 reg = <0xff293000 0x20>; 692 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru PCLK_MAILBOX>; 694 clock-names = "pclk_mailbox"; 695 #mbox-cells = <1>; 696 status = "disabled"; 697 }; 698 699 usb2phy: usb2-phy@ff2b0000 { 700 compatible = "rockchip,rk3506-usb2phy"; 701 reg = <0xff2b0000 0x8000>; 702 clocks = <&cru CLK_REF_USBPHY_TOP>, <&cru PCLK_USBPHY>; 703 clock-names = "phyclk", "apb_pclk"; 704 #clock-cells = <0>; 705 rockchip,usbgrf = <&grf>; 706 status = "disabled"; 707 708 u2phy_otg0: otg-port { 709 #phy-cells = <0>; 710 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 713 interrupt-names = "otg-bvalid", 714 "otg-id", 715 "linestate"; 716 status = "disabled"; 717 }; 718 719 u2phy_otg1: host-port { 720 #phy-cells = <0>; 721 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-names = "otg-bvalid", 725 "otg-id", 726 "linestate"; 727 status = "disabled"; 728 }; 729 }; 730 731 sai0: sai@ff300000 { 732 compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; 733 reg = <0xff300000 0x1000>; 734 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; 736 clock-names = "mclk", "hclk"; 737 dmas = <&dmac1 1 0xff2880a4 0x01000000 0x0 0x0>, 738 <&dmac1 0 0xff2880a4 0x00800000 0x0 0x0>; 739 // dmas = <&dmac0 9 0xff2880a4 0x01000100 0xff2880ac 0x000c0000>, 740 // <&dmac0 8 0xff2880a4 0x00800080 0xff2880ac 0x00030002>; 741 dma-names = "tx", "rx"; 742 resets = <&cru SRST_M_SAI0>, <&cru SRST_H_SAI0>; 743 reset-names = "m", "h"; 744 #sound-dai-cells = <0>; 745 sound-name-prefix = "SAI0"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&sai0_lrck_pins 748 &sai0_sclk_pins 749 &sai0_sdi0_pins 750 &sai0_sdi1_pins 751 &sai0_sdi2_pins 752 &sai0_sdi3_pins 753 &sai0_sdo_pins>; 754 status = "disabled"; 755 }; 756 757 sai1: sai@ff310000 { 758 compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; 759 reg = <0xff310000 0x1000>; 760 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; 762 clock-names = "mclk", "hclk"; 763 dmas = <&dmac1 3 0xff2880a4 0x04000000 0x0 0x0>, 764 <&dmac1 2 0xff2880a4 0x02000000 0x0 0x0>; 765 // dmas = <&dmac0 11 0xff2880a4 0x04000400 0xff2880ac 0x00c00000>, 766 // <&dmac0 10 0xff2880a4 0x02000200 0xff2880ac 0x00300020>; 767 dma-names = "tx", "rx"; 768 resets = <&cru SRST_M_SAI1>, <&cru SRST_H_SAI1>; 769 reset-names = "m", "h"; 770 #sound-dai-cells = <0>; 771 sound-name-prefix = "SAI1"; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&sai1_lrck_pins 774 &sai1_sclk_pins 775 &sai1_sdi_pins 776 &sai1_sdo0_pins 777 &sai1_sdo1_pins 778 &sai1_sdo2_pins 779 &sai1_sdo3_pins>; 780 status = "disabled"; 781 }; 782 783 can0: can@ff320000 { 784 compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; 785 reg = <0xff320000 0x1000>; 786 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; 788 clock-names = "baudclk", "apb_pclk"; 789 resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>; 790 reset-names = "can", "can-apb"; 791 status = "disabled"; 792 }; 793 794 can1: can@ff330000 { 795 compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; 796 reg = <0xff330000 0x1000>; 797 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; 799 clock-names = "baudclk", "apb_pclk"; 800 resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>; 801 reset-names = "can", "can-apb"; 802 status = "disabled"; 803 }; 804 805 pdm: pdm@ff380000 { 806 compatible = "rockchip,rk3506-pdm", "rockchip,rk3576-pdm"; 807 reg = <0xff380000 0x1000>; 808 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; 810 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 811 dmas = <&dmac1 9 0xff2880a4 0x00100000 0x0 0x0>; 812 // dmas = <&dmac0 5 0xff2880a4 0x00100010 0xff2880a8 0x0c000800>; 813 dma-names = "rx"; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&rm_io0_pdm_clk0 816 &rm_io0_pdm_clk1 817 &rm_io0_pdm_sdi0 818 &rm_io0_pdm_sdi1 819 &rm_io0_pdm_sdi2 820 &rm_io0_pdm_sdi3>; 821 #sound-dai-cells = <0>; 822 sound-name-prefix = "PDM0"; 823 status = "disabled"; 824 }; 825 826 spdif_tx: spdif-tx@ff3a0000 { 827 compatible = "rockchip,rk3506-spdif", "rockchip,rk3066-spdif"; 828 reg = <0xff3a0000 0x1000>; 829 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cru MCLK_SPDIFTX>, <&cru HCLK_SPDIFTX>; 831 clock-names = "mclk", "hclk"; 832 dmas = <&dmac1 10 0xff2880a4 0x00200000 0xff2880ac 0x03000100>; 833 // dmas = <&dmac0 6 0xff2880a4 0x00200020 0xff2880a8 0x30000000>; 834 dma-names = "tx"; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&rm_io0_spdif_tx>; 837 #sound-dai-cells = <0>; 838 status = "disabled"; 839 }; 840 841 spdif_rx: spdif-rx@ff3b0000 { 842 compatible = "rockchip,rk3506-spdifrx", "rockchip,rk3308-spdifrx"; 843 reg = <0xff3b0000 0x1000>; 844 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cru MCLK_SPDIFRX>, <&cru HCLK_SPDIFRX>; 846 clock-names = "mclk", "hclk"; 847 dmas = <&dmac1 11 0xff2880a4 0x00400000 0xff2880ac 0x0c000400>; 848 // dmas = <&dmac0 7 0xff2880a4 0x00400040 0xff2880a8 0xc0000000>; 849 dma-names = "rx"; 850 resets = <&cru SRST_SPDIFRX>; 851 reset-names = "spdifrx-m"; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&rm_io0_spdif_rx>; 854 #sound-dai-cells = <0>; 855 status = "disabled"; 856 }; 857 858 mmc: mmc@ff480000 { 859 compatible = "rockchip,rk3506-dw-mshc", "rockchip,rk3288-dw-mshc"; 860 reg = <0xff480000 0x4000>; 861 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 862 max-frequency = <150000000>; 863 bus-width = <4>; 864 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>; 865 clock-names = "biu", "ciu"; 866 fifo-depth = <0x100>; 867 resets = <&cru SRST_H_SDMMC>; 868 reset-names = "reset"; 869 status = "disabled"; 870 }; 871 872 fspi: spi@ff488000 { 873 compatible = "rockchip,fspi"; 874 reg = <0xff488000 0x4000>; 875 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&cru SCLK_FSPI>, <&cru HCLK_FSPI>; 877 clock-names = "clk_sfc", "hclk_sfc"; 878 rockchip,max-dll = <0x17F>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 status = "disabled"; 882 }; 883 884 sai2: sai@ff498000 { 885 compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; 886 reg = <0xff498000 0x1000>; 887 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; 889 clock-names = "mclk", "hclk"; 890 dmas = <&dmac1 5 0x0 0x0 0x0 0x0>, <&dmac1 4 0x0 0x0 0x0 0x0>; 891 dma-names = "tx", "rx"; 892 resets = <&cru SRST_M_SAI2>, <&cru SRST_H_SAI2>; 893 reset-names = "m", "h"; 894 #sound-dai-cells = <0>; 895 sound-name-prefix = "SAI2"; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&sai2m0_lrck_pins 898 &sai2m0_sclk_pins 899 &sai2m0_sdi_pins 900 &sai2m0_sdo_pins>; 901 status = "disabled"; 902 }; 903 904 sai3: sai@ff4a0000 { 905 compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; 906 reg = <0xff4a0000 0x1000>; 907 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&cru MCLK_SAI3>, <&cru HCLK_SAI3>; 909 clock-names = "mclk", "hclk"; 910 dmas = <&dmac1 6 0x0 0x0 0x0 0x0>, <&dmac1 7 0x0 0x0 0x0 0x0>; 911 dma-names = "tx", "rx"; 912 resets = <&cru SRST_M_SAI3>, <&cru SRST_H_SAI3>; 913 reset-names = "m", "h"; 914 #sound-dai-cells = <0>; 915 sound-name-prefix = "SAI3"; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&sai3_lrck_pins 918 &sai3_sclk_pins 919 &sai3_sdi_pins 920 &sai3_sdo_pins>; 921 status = "disabled"; 922 }; 923 924 sai4: sai@ff4a8000 { 925 compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; 926 reg = <0xff4a8000 0x1000>; 927 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cru MCLK_SAI4>, <&cru HCLK_SAI4>; 929 clock-names = "mclk", "hclk"; 930 dmas = <&dmac1 8 0x0 0x0 0x0 0x0>; 931 dma-names = "rx"; 932 resets = <&cru SRST_M_SAI4>, <&cru SRST_H_SAI4>; 933 reset-names = "m", "h"; 934 #sound-dai-cells = <0>; 935 sound-name-prefix = "SAI4"; 936 status = "disabled"; 937 }; 938 939 acdcdig_dsm: acdcdig-dsm@ff4b0000 { 940 compatible = "rockchip,rk3506-dsm"; 941 reg = <0xff4b0000 0x1000>; 942 clocks = <&cru MCLK_DSM>, <&cru HCLK_DSM>; 943 clock-names = "dac", "pclk"; 944 resets = <&cru SRST_M_DSM>; 945 reset-names = "reset" ; 946 rockchip,grf = <&grf>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&dsm_audm0_ln_pins 949 &dsm_audm0_lp_pins 950 &dsm_audm0_rn_pins 951 &dsm_audm0_rp_pins>; 952 #sound-dai-cells = <0>; 953 status = "disabled"; 954 }; 955 956 gmac0: ethernet@ff4c8000 { 957 compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a"; 958 reg = <0xff4c8000 0x2000>; 959 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "macirq", "eth_wake_irq"; 962 rockchip,grf = <&grf>; 963 clocks = <&cru CLK_MAC0>, <&cru CLK_MAC0_PTP>, 964 <&cru PCLK_MAC0>, <&cru ACLK_MAC0>; 965 clock-names = "stmmaceth", "ptp_ref", 966 "pclk_mac", "aclk_mac"; 967 resets = <&cru SRST_A_MAC0>; 968 reset-names = "stmmaceth"; 969 970 snps,mixed-burst; 971 snps,tso; 972 973 snps,axi-config = <&gmac0_stmmac_axi_setup>; 974 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 975 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 976 977 phy-mode = "rmii"; 978 status = "disabled"; 979 980 mdio0: mdio { 981 compatible = "snps,dwmac-mdio"; 982 #address-cells = <0x1>; 983 #size-cells = <0x0>; 984 }; 985 986 gmac0_stmmac_axi_setup: stmmac-axi-config { 987 snps,wr_osr_lmt = <4>; 988 snps,rd_osr_lmt = <8>; 989 snps,blen = <0 0 0 0 16 8 4>; 990 }; 991 992 gmac0_mtl_rx_setup: rx-queues-config { 993 snps,rx-queues-to-use = <1>; 994 queue0 { 995 status = "okay"; 996 }; 997 }; 998 999 gmac0_mtl_tx_setup: tx-queues-config { 1000 snps,tx-queues-to-use = <1>; 1001 queue0 { 1002 status = "okay"; 1003 }; 1004 }; 1005 }; 1006 1007 gmac1: ethernet@ff4d0000 { 1008 compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a"; 1009 reg = <0xff4d0000 0x2000>; 1010 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1012 interrupt-names = "macirq", "eth_wake_irq"; 1013 rockchip,grf = <&grf>; 1014 clocks = <&cru CLK_MAC1>, <&cru CLK_MAC1_PTP>, 1015 <&cru PCLK_MAC1>, <&cru ACLK_MAC1>; 1016 clock-names = "stmmaceth", "ptp_ref", 1017 "pclk_mac", "aclk_mac"; 1018 resets = <&cru SRST_A_MAC1>; 1019 reset-names = "stmmaceth"; 1020 1021 snps,mixed-burst; 1022 snps,tso; 1023 1024 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1025 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1026 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1027 1028 phy-mode = "rmii"; 1029 status = "disabled"; 1030 1031 mdio1: mdio { 1032 compatible = "snps,dwmac-mdio"; 1033 #address-cells = <0x1>; 1034 #size-cells = <0x0>; 1035 }; 1036 1037 gmac1_stmmac_axi_setup: stmmac-axi-config { 1038 snps,wr_osr_lmt = <4>; 1039 snps,rd_osr_lmt = <8>; 1040 snps,blen = <0 0 0 0 16 8 4>; 1041 }; 1042 1043 gmac1_mtl_rx_setup: rx-queues-config { 1044 snps,rx-queues-to-use = <1>; 1045 queue0 { 1046 status = "okay"; 1047 }; 1048 }; 1049 1050 gmac1_mtl_tx_setup: tx-queues-config { 1051 snps,tx-queues-to-use = <1>; 1052 queue0 { 1053 status = "okay"; 1054 }; 1055 }; 1056 }; 1057 1058 ioc_grf: syscon@ff4d8000 { 1059 compatible = "rockchip,rk3506-ioc-grf", "syscon"; 1060 reg = <0xff4d8000 0x8000>; 1061 }; 1062 1063 uart5: serial@ff4e0000 { 1064 compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; 1065 reg = <0xff4e0000 0x100>; 1066 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1067 reg-shift = <2>; 1068 reg-io-width = <4>; 1069 dmas = <&dmac1 14 0x0 0x0 0x0 0x0>, <&dmac1 15 0x0 0x0 0x0 0x0>; 1070 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1071 clock-names = "baudclk", "apb_pclk"; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; 1074 status = "disabled"; 1075 }; 1076 1077 saradc: adc@ff4e8000 { 1078 compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc"; 1079 reg = <0xff4e8000 0x8000>; 1080 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1081 #io-channel-cells = <1>; 1082 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1083 clock-names = "saradc", "apb_pclk"; 1084 resets = <&cru SRST_P_SARADC>; 1085 reset-names = "saradc-apb"; 1086 status = "disabled"; 1087 }; 1088 1089 otp: otp@ff4f0000 { 1090 compatible = "rockchip,rk3506-otp"; 1091 reg = <0xff4f0000 0x4000>; 1092 #address-cells = <1>; 1093 #size-cells = <1>; 1094 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 1095 <&cru PCLK_OTPC_NS>; 1096 clock-names = "usr", "sbpi", "apb"; 1097 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 1098 <&cru SRST_P_OTPC_NS>; 1099 reset-names = "usr", "sbpi", "apb"; 1100 1101 /* Data cells */ 1102 cpu_code: cpu-code@2 { 1103 reg = <0x02 0x2>; 1104 }; 1105 otp_cpu_version: cpu-version@5 { 1106 reg = <0x05 0x1>; 1107 bits = <3 3>; 1108 }; 1109 otp_id: id@a { 1110 reg = <0x0a 0x10>; 1111 }; 1112 cpu_leakage: cpu-leakage@1e { 1113 reg = <0x1e 0x1>; 1114 }; 1115 log_leakage: log-leakage@1f { 1116 reg = <0x1f 0x1>; 1117 }; 1118 }; 1119 1120 audio_codec: audio-codec@ff4f8000 { 1121 compatible = "rockchip,rk3506-codec"; 1122 reg = <0xff4f8000 0x1000>; 1123 #sound-dai-cells = <0>; 1124 clocks = <&cru PCLK_AUDIO_ADC>, <&cru MCLK_AUDIO_ADC>; 1125 clock-names = "pclk", "mclk"; 1126 resets = <&cru SRST_M_AUDIO_ADC>; 1127 reset-names = "rst"; 1128 status = "disabled"; 1129 }; 1130 1131 gic: interrupt-controller@ff581000 { 1132 compatible = "arm,gic-400"; 1133 reg = <0xff581000 0x1000>, 1134 <0xff582000 0x2000>, 1135 <0xff584000 0x2000>, 1136 <0xff586000 0x2000>; 1137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1138 #interrupt-cells = <3>; 1139 interrupt-controller; 1140 #address-cells = <0>; 1141 }; 1142 1143 vop: vop@ff600000 { 1144 compatible = "rockchip,rk3506-vop"; 1145 reg = <0xff600000 0x200>, <0xff600a00 0x400>; 1146 reg-names = "regs", "gamma_lut"; 1147 rockchip,grf = <&grf>; 1148 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1150 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1151 status = "disabled"; 1152 1153 vop_out: port { 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 vop_out_rgb: endpoint@0 { 1158 reg = <0>; 1159 remote-endpoint = <&rgb_in_vop>; 1160 }; 1161 1162 vop_out_dsi: endpoint@1 { 1163 reg = <1>; 1164 remote-endpoint = <&dsi_in_vop>; 1165 }; 1166 }; 1167 }; 1168 1169 rga2: rga@ff610000 { 1170 compatible = "rockchip,rga2"; 1171 reg = <0xff610000 0x1000>; 1172 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1173 interrupt-names = "rga2_irq"; 1174 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; 1175 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1176 status = "disabled"; 1177 }; 1178 1179 dsi: dsi@ff640000 { 1180 compatible = "rockchip,rk3506-mipi-dsi"; 1181 reg = <0xff640000 0x10000>; 1182 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&cru PCLK_DSI_HOST>; 1184 clock-names = "pclk"; 1185 resets = <&cru SRST_P_DSI_HOST>; 1186 reset-names = "apb"; 1187 phys = <&dsi_dphy>; 1188 phy-names = "dphy"; 1189 rockchip,grf = <&grf>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 1194 ports { 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 1198 dsi_in: port@0 { 1199 reg = <0>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 dsi_in_vop: endpoint@0 { 1203 reg = <0>; 1204 remote-endpoint = <&vop_out_dsi>; 1205 status = "disabled"; 1206 }; 1207 }; 1208 }; 1209 }; 1210 1211 tsadc: tsadc@ff650000 { 1212 compatible = "rockchip,rk3506-tsadc"; 1213 reg = <0xff650000 0x400>; 1214 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; 1216 clock-names = "tsadc", "apb_pclk", "tsen"; 1217 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 1218 assigned-clock-rates = <1000000>, <12000000>; 1219 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 1220 reset-names = "tsadc", "tsadc-apb"; 1221 #thermal-sensor-cells = <1>; 1222 rockchip,grf = <&grf>; 1223 rockchip,hw-tshut-temp = <120000>; 1224 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1225 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1226 status = "disabled"; 1227 }; 1228 1229 ioc1: syscon@ff660000 { 1230 compatible = "rockchip,rk3506-ioc1", "syscon"; 1231 reg = <0xff660000 0x10000>; 1232 }; 1233 1234 dsi_dphy: phy@ff670000 { 1235 compatible = "rockchip,rk3506-dsi-dphy"; 1236 reg = <0xff670000 0x10000>, 1237 <0xff640000 0x10000>; 1238 reg-names = "phy", "host"; 1239 clocks = <&cru CLK_REF_DPHY_TOP>, 1240 <&cru PCLK_DPHY>, <&cru PCLK_DSI_HOST>; 1241 clock-names = "ref", "pclk", "pclk_host"; 1242 #clock-cells = <0>; 1243 resets = <&cru SRST_P_DPHY>; 1244 reset-names = "apb"; 1245 #phy-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 crypto: crypto@ff700000 { 1250 compatible = "rockchip,crypto-v4"; 1251 reg = <0xff700000 0x2000>; 1252 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, 1254 <&cru CLK_CORE_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; 1255 clock-names = "aclk", "hclk", "core", "pka"; 1256 resets = <&cru SRST_H_CRYPTO>; 1257 reset-names = "crypto-rst"; 1258 status = "disabled"; 1259 }; 1260 1261 rng: rng@ff710000 { 1262 compatible = "rockchip,rkrng"; 1263 reg = <0xff710000 0x200>; 1264 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cru HCLK_RNG>; 1266 clock-names = "hclk_trng"; 1267 resets = <&cru SRST_H_RNG>; 1268 reset-names = "reset"; 1269 status = "disabled"; 1270 }; 1271 1272 usb20_otg0: usb@ff740000 { 1273 compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", 1274 "snps,dwc2"; 1275 reg = <0xff740000 0x40000>; 1276 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cru HCLK_USBOTG0>, <&cru HCLK_USBOTG0_PMU>, 1278 <&cru CLK_USBOTG0_ADP>; 1279 clock-names = "otg", "pmu", "adp"; 1280 dr_mode = "otg"; 1281 phys = <&u2phy_otg0>; 1282 phy-names = "usb2-phy"; 1283 g-np-tx-fifo-size = <16>; 1284 g-rx-fifo-size = <280>; 1285 g-tx-fifo-size = <256 128 128 64 32 16>; 1286 status = "disabled"; 1287 }; 1288 1289 usb20_otg1: usb@ff780000 { 1290 compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", 1291 "snps,dwc2"; 1292 reg = <0xff780000 0x40000>; 1293 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cru HCLK_USBOTG1>, <&cru HCLK_USBOTG1_PMU>, 1295 <&cru CLK_USBOTG1_ADP>; 1296 clock-names = "otg", "pmu", "adp"; 1297 dr_mode = "otg"; 1298 phys = <&u2phy_otg1>; 1299 phy-names = "usb2-phy"; 1300 g-np-tx-fifo-size = <16>; 1301 g-rx-fifo-size = <280>; 1302 g-tx-fifo-size = <256 128 128 64 32 16>; 1303 status = "disabled"; 1304 }; 1305 1306 arm-debug@ff810000 { 1307 compatible = "rockchip,debug"; 1308 reg = <0xff810000 0x1000>, 1309 <0xff812000 0x1000>, 1310 <0xff814000 0x1000>; 1311 }; 1312 1313 flexbus: flexbus@ff880000 { 1314 compatible = "rockchip,rk3506-flexbus"; 1315 reg = <0xff880000 0x200>; 1316 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&cru CLK_FLEXBUS_TX>, <&cru CLK_FLEXBUS_RX>, 1318 <&cru ACLK_FLEXBUS>, <&cru HCLK_FLEXBUS>; 1319 clock-names = "tx_clk_flexbus", "rx_clk_flexbus", 1320 "aclk_flexbus", "hclk_flexbus"; 1321 rockchip,grf = <&grf>; 1322 status = "disabled"; 1323 1324 flexbus_adc: adc { 1325 compatible = "rockchip,flexbus-adc"; 1326 #io-channel-cells = <0>; 1327 rockchip,slave-mode; 1328 rockchip,free-sclk; 1329 rockchip,auto-pad; 1330 rockchip,dfs = <16>; 1331 status = "disabled"; 1332 }; 1333 1334 flexbus_cif: cif { 1335 compatible = "rockchip,flexbus-cif-rk3506"; 1336 status = "disabled"; 1337 }; 1338 1339 flexbus_dac: dac { 1340 compatible = "rockchip,flexbus-dac"; 1341 #io-channel-cells = <0>; 1342 rockchip,free-sclk; 1343 rockchip,dfs = <16>; 1344 status = "disabled"; 1345 }; 1346 1347 flexbus_fspi: fspi { 1348 compatible = "rockchip,flexbus-fspi"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 status = "disabled"; 1352 }; 1353 }; 1354 1355 dsmc_lb_slave: dsmc-lb-slave@ff880000 { 1356 compatible = "rockchip,rk3506-dsmc-lb-slave"; 1357 reg = <0xff880000 0x10000>; 1358 #address-cells = <1>; 1359 #size-cells = <1>; 1360 rockchip,grf = <&grf>; 1361 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1362 resets = <&cru SRST_DSMC_SLV>, <&cru SRST_A_DSMC_SLV>, 1363 <&cru SRST_H_DSMC_SLV>; 1364 reset-names = "dsmc_slv", "a_dsmc_slv", "h_dsmc_slv"; 1365 clocks = <&cru ACLK_DSMC_SLV>, 1366 <&cru HCLK_DSMC_SLV>; 1367 clock-names = "aclk_dsmc_slv", "hclk_dsmc_slv"; 1368 status = "disabled"; 1369 }; 1370 1371 dsmc: dsmc@ff8b0000 { 1372 compatible = "rockchip,rk3506-dsmc"; 1373 reg = <0xff8b0000 0x10000>; 1374 #address-cells = <1>; 1375 #size-cells = <1>; 1376 rockchip,grf = <&ioc_grf>; 1377 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1378 resets = <&cru SRST_A_DSMC>, <&cru SRST_P_DSMC>; 1379 reset-names = "dsmc", "apb"; 1380 clocks = <&cru CLK_DSMC>, 1381 <&cru ACLK_DSMC>, 1382 <&cru PCLK_DSMC>, 1383 <&cru CLK_DSMC>; 1384 clock-names = "clk_sys", "aclk_dsmc", "pclk", "aclk_root"; 1385 clock-frequency = <100000000>; 1386 dmas = <&dmac0 2 0xff288078 0x80000000 0xff2880a8 0x00300000>, 1387 <&dmac0 3 0xff288078 0x40000000 0xff2880a8 0x00c00000>; 1388 // dmas = <&dmac0 8 0xff288078 0x80008000 0xff2880ac 0x00030000>, 1389 // <&dmac0 10 0xff288078 0x40004000 0xff2880ac 0x00300000>; 1390 dma-names = "req0", "req1"; 1391 status = "disabled"; 1392 slave { 1393 rockchip,dqs-dll = <0x40 0x40 1394 0x40 0x40 1395 0x40 0x40 1396 0x40 0x40>; 1397 rockchip,ranges = <0x0 0xc0000000 0x0 0x2000000>; 1398 rockchip,slave-dev = <&dsmc_slave>; 1399 }; 1400 }; 1401 1402 dsmc_slave: dsmc-slave { 1403 compatible = "rockchip,dsmc-slave"; 1404 rockchip,clk-mode = <0>; 1405 status = "disabled"; 1406 psram { 1407 dsmc_psram0: psram0 { 1408 status = "disabled"; 1409 }; 1410 dsmc_psram1: psram1 { 1411 status = "disabled"; 1412 }; 1413 dsmc_psram2: psram2 { 1414 status = "disabled"; 1415 }; 1416 dsmc_psram3: psram3 { 1417 status = "disabled"; 1418 }; 1419 }; 1420 1421 lb-slave { 1422 dsmc_lb_slave0: lb-slave0 { 1423 status = "disabled"; 1424 dsmc_p0_region: region { 1425 dsmc_p0_region0: region0 { 1426 rockchip,attribute = "Merged FIFO"; 1427 rockchip,ca-addr-width = <0>; 1428 rockchip,dummy-clk-num = <1>; 1429 rockchip,cs0-be-ctrled = <0>; 1430 rockchip,cs0-ctrl = <0>; 1431 status = "disabled"; 1432 }; 1433 dsmc_p0_region1: region1 { 1434 rockchip,attribute = "No-Merge FIFO"; 1435 rockchip,ca-addr-width = <0>; 1436 rockchip,dummy-clk-num = <1>; 1437 rockchip,cs0-be-ctrled = <0>; 1438 rockchip,cs0-ctrl = <0>; 1439 status = "disabled"; 1440 }; 1441 dsmc_p0_region2: region2 { 1442 rockchip,attribute = "DPRA"; 1443 rockchip,ca-addr-width = <0>; 1444 rockchip,dummy-clk-num = <1>; 1445 rockchip,cs0-be-ctrled = <0>; 1446 rockchip,cs0-ctrl = <0>; 1447 status = "disabled"; 1448 }; 1449 dsmc_p0_region3: region3 { 1450 rockchip,attribute = "Register"; 1451 rockchip,ca-addr-width = <0>; 1452 rockchip,dummy-clk-num = <1>; 1453 rockchip,cs0-be-ctrled = <0>; 1454 rockchip,cs0-ctrl = <0>; 1455 status = "disabled"; 1456 }; 1457 }; 1458 }; 1459 dsmc_lb_slave1: lb-slave1 { 1460 status = "disabled"; 1461 dsmc_p1_region: region { 1462 dsmc_p1_region0: region0 { 1463 rockchip,attribute = "Merged FIFO"; 1464 rockchip,ca-addr-width = <0>; 1465 rockchip,dummy-clk-num = <1>; 1466 rockchip,cs0-be-ctrled = <0>; 1467 rockchip,cs0-ctrl = <0>; 1468 status = "disabled"; 1469 }; 1470 dsmc_p1_region1: region1 { 1471 rockchip,attribute = "No-Merge FIFO"; 1472 rockchip,ca-addr-width = <0>; 1473 rockchip,dummy-clk-num = <1>; 1474 rockchip,cs0-be-ctrled = <0>; 1475 rockchip,cs0-ctrl = <0>; 1476 status = "disabled"; 1477 }; 1478 dsmc_p1_region2: region2 { 1479 rockchip,attribute = "DPRA"; 1480 rockchip,ca-addr-width = <0>; 1481 rockchip,dummy-clk-num = <1>; 1482 rockchip,cs0-be-ctrled = <0>; 1483 rockchip,cs0-ctrl = <0>; 1484 status = "disabled"; 1485 }; 1486 dsmc_p1_region3: region3 { 1487 rockchip,attribute = "Register"; 1488 rockchip,ca-addr-width = <0>; 1489 rockchip,dummy-clk-num = <1>; 1490 rockchip,cs0-be-ctrled = <0>; 1491 rockchip,cs0-ctrl = <0>; 1492 status = "disabled"; 1493 }; 1494 }; 1495 }; 1496 dsmc_lb_slave2: lb-slave2 { 1497 status = "disabled"; 1498 dsmc_p2_region: region { 1499 dsmc_p2_region0: region0 { 1500 rockchip,attribute = "Merged FIFO"; 1501 rockchip,ca-addr-width = <0>; 1502 rockchip,dummy-clk-num = <1>; 1503 rockchip,cs0-be-ctrled = <0>; 1504 rockchip,cs0-ctrl = <0>; 1505 status = "disabled"; 1506 }; 1507 dsmc_p2_region1: region1 { 1508 rockchip,attribute = "No-Merge FIFO"; 1509 rockchip,ca-addr-width = <0>; 1510 rockchip,dummy-clk-num = <1>; 1511 rockchip,cs0-be-ctrled = <0>; 1512 rockchip,cs0-ctrl = <0>; 1513 status = "disabled"; 1514 }; 1515 dsmc_p2_region2: region2 { 1516 rockchip,attribute = "DPRA"; 1517 rockchip,ca-addr-width = <0>; 1518 rockchip,dummy-clk-num = <1>; 1519 rockchip,cs0-be-ctrled = <0>; 1520 rockchip,cs0-ctrl = <0>; 1521 status = "disabled"; 1522 }; 1523 dsmc_p2_region3: region3 { 1524 rockchip,attribute = "Register"; 1525 rockchip,ca-addr-width = <0>; 1526 rockchip,dummy-clk-num = <1>; 1527 rockchip,cs0-be-ctrled = <0>; 1528 rockchip,cs0-ctrl = <0>; 1529 status = "disabled"; 1530 }; 1531 }; 1532 }; 1533 dsmc_lb_slave3: lb-slave3 { 1534 status = "disabled"; 1535 dsmc_p3_region: region { 1536 dsmc_p3_region0: region0 { 1537 rockchip,attribute = "Merged FIFO"; 1538 rockchip,ca-addr-width = <0>; 1539 rockchip,dummy-clk-num = <1>; 1540 rockchip,cs0-be-ctrled = <0>; 1541 rockchip,cs0-ctrl = <0>; 1542 status = "disabled"; 1543 }; 1544 dsmc_p3_region1: region1 { 1545 rockchip,attribute = "No-Merge FIFO"; 1546 rockchip,ca-addr-width = <0>; 1547 rockchip,dummy-clk-num = <1>; 1548 rockchip,cs0-be-ctrled = <0>; 1549 rockchip,cs0-ctrl = <0>; 1550 status = "disabled"; 1551 }; 1552 dsmc_p3_region2: region2 { 1553 rockchip,attribute = "DPRA"; 1554 rockchip,ca-addr-width = <0>; 1555 rockchip,dummy-clk-num = <1>; 1556 rockchip,cs0-be-ctrled = <0>; 1557 rockchip,cs0-ctrl = <0>; 1558 status = "disabled"; 1559 }; 1560 dsmc_p3_region3: region3 { 1561 rockchip,attribute = "Register"; 1562 rockchip,ca-addr-width = <0>; 1563 rockchip,dummy-clk-num = <1>; 1564 rockchip,cs0-be-ctrled = <0>; 1565 rockchip,cs0-ctrl = <0>; 1566 status = "disabled"; 1567 }; 1568 }; 1569 }; 1570 }; 1571 }; 1572 1573 grf_pmu: syscon@ff910000 { 1574 compatible = "rockchip,rk3506-grf-pmu", "syscon", "simple-mfd"; 1575 reg = <0xff910000 0x4000>; 1576 1577 reboot_mode: reboot-mode { 1578 compatible = "syscon-reboot-mode"; 1579 offset = <0x200>; 1580 mode-bootloader = <BOOT_BL_DOWNLOAD>; 1581 mode-charge = <BOOT_CHARGING>; 1582 mode-fastboot = <BOOT_FASTBOOT>; 1583 mode-loader = <BOOT_BL_DOWNLOAD>; 1584 mode-normal = <BOOT_NORMAL>; 1585 mode-recovery = <BOOT_RECOVERY>; 1586 mode-ums = <BOOT_UMS>; 1587 mode-panic = <BOOT_PANIC>; 1588 mode-watchdog = <BOOT_WATCHDOG>; 1589 }; 1590 }; 1591 1592 pwm0_4ch_0: pwm@ff930000 { 1593 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 1594 reg = <0xff930000 0x200>; 1595 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1596 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1597 clock-names = "pwm", "pclk"; 1598 #pwm-cells = <3>; 1599 status = "disabled"; 1600 }; 1601 1602 pwm0_4ch_1: pwm@ff931000 { 1603 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 1604 reg = <0xff931000 0x200>; 1605 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1607 clock-names = "pwm", "pclk"; 1608 #pwm-cells = <3>; 1609 status = "disabled"; 1610 }; 1611 1612 pwm0_4ch_2: pwm@ff932000 { 1613 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 1614 reg = <0xff932000 0x200>; 1615 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1616 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1617 clock-names = "pwm", "pclk"; 1618 #pwm-cells = <3>; 1619 status = "disabled"; 1620 }; 1621 1622 pwm0_4ch_3: pwm@ff933000 { 1623 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; 1624 reg = <0xff933000 0x200>; 1625 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1627 clock-names = "pwm", "pclk"; 1628 #pwm-cells = <3>; 1629 status = "disabled"; 1630 }; 1631 1632 ioc_pmu: syscon@ff950000 { 1633 compatible = "rockchip,rk3506-ioc-pmu", "syscon"; 1634 reg = <0xff950000 0x10000>; 1635 }; 1636 1637 cru: clock-controller@ff9a0000 { 1638 compatible = "rockchip,rk3506-cru"; 1639 reg = <0xff9a0000 0x20000>; 1640 rockchip,grf = <&grf>; 1641 #clock-cells = <1>; 1642 #reset-cells = <1>; 1643 }; 1644 1645 pinctrl: pinctrl { 1646 compatible = "rockchip,rk3506-pinctrl"; 1647 rockchip,grf = <&ioc_grf>; 1648 rockchip,ioc1 = <&ioc1>; 1649 rockchip,pmu = <&ioc_pmu>; 1650 rockchip,rmio = <&grf_pmu>; 1651 #address-cells = <1>; 1652 #size-cells = <1>; 1653 ranges; 1654 1655 gpio0: gpio@ff940000 { 1656 compatible = "rockchip,gpio-bank"; 1657 reg = <0xff940000 0x200>; 1658 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1660 1661 gpio-controller; 1662 #gpio-cells = <2>; 1663 gpio-ranges = <&pinctrl 0 0 32>; 1664 interrupt-controller; 1665 #interrupt-cells = <2>; 1666 }; 1667 1668 gpio1: gpio@ff870000 { 1669 compatible = "rockchip,gpio-bank"; 1670 reg = <0xff870000 0x200>; 1671 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1672 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1673 1674 gpio-controller; 1675 #gpio-cells = <2>; 1676 gpio-ranges = <&pinctrl 0 32 32>; 1677 interrupt-controller; 1678 #interrupt-cells = <2>; 1679 }; 1680 1681 gpio2: gpio@ff1c0000 { 1682 compatible = "rockchip,gpio-bank"; 1683 reg = <0xff1c0000 0x200>; 1684 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1685 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1686 1687 gpio-controller; 1688 #gpio-cells = <2>; 1689 gpio-ranges = <&pinctrl 0 64 32>; 1690 interrupt-controller; 1691 #interrupt-cells = <2>; 1692 }; 1693 1694 gpio3: gpio@ff1d0000 { 1695 compatible = "rockchip,gpio-bank"; 1696 reg = <0xff1d0000 0x200>; 1697 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1698 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1699 1700 gpio-controller; 1701 #gpio-cells = <2>; 1702 gpio-ranges = <&pinctrl 0 96 32>; 1703 interrupt-controller; 1704 #interrupt-cells = <2>; 1705 }; 1706 1707 gpio4: gpio@ff1e0000 { 1708 compatible = "rockchip,gpio-bank"; 1709 reg = <0xff1e0000 0x200>; 1710 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1712 1713 gpio-controller; 1714 #gpio-cells = <2>; 1715 gpio-ranges = <&pinctrl 0 128 32>; 1716 interrupt-controller; 1717 #interrupt-cells = <2>; 1718 }; 1719 }; 1720}; 1721 1722#include "rk3506-pinctrl.dtsi" 1723#include "rk3506-pinctrl-rmio.dtsi" 1724
