1 #ifndef __ODY_CSRS_XCP_H__
2 #define __ODY_CSRS_XCP_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * XCP.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration xcp_addr_prt_e
24 *
25 * XCP Address Partition Enumeration
26 * Enumerates the partitions in CM7 address space, as recorded in XCP()_PRECISE_BUS_ERR_STATUS[PART].
27 */
28 #define ODY_XCP_ADDR_PRT_E_CSR_CPC (3)
29 #define ODY_XCP_ADDR_PRT_E_CSR_PSBM (4)
30 #define ODY_XCP_ADDR_PRT_E_CSR_XCP (2)
31 #define ODY_XCP_ADDR_PRT_E_MEM (1)
32 #define ODY_XCP_ADDR_PRT_E_NCB (5)
33 #define ODY_XCP_ADDR_PRT_E_NONE (0)
34 #define ODY_XCP_ADDR_PRT_E_RML (6)
35
36 /**
37 * Enumeration xcp_bar_e
38 *
39 * XCP Base Address Register Enumeration
40 * Enumerates the base address registers.
41 */
42 #define ODY_XCP_BAR_E_XCPX_PF_BAR0(a) (0x82c000000000ll + 0x1000000000ll * (a))
43 #define ODY_XCP_BAR_E_XCPX_PF_BAR0_SIZE 0x100000ull
44 #define ODY_XCP_BAR_E_XCPX_PF_BAR4(a) (0x82c000100000ll + 0x1000000000ll * (a))
45 #define ODY_XCP_BAR_E_XCPX_PF_BAR4_SIZE 0x100000ull
46
47 /**
48 * Enumeration xcp_cm7_vec_int_e
49 *
50 * XCP CM7 Vectored Interrupt Enumeration
51 * Enumerates the vectored interrupt inputs to the CM7 core.
52 */
53 #define ODY_XCP_CM7_VEC_INT_E_BUS_ERR (0)
54 #define ODY_XCP_CM7_VEC_INT_E_CTIIRQ0 (6)
55 #define ODY_XCP_CM7_VEC_INT_E_CTIIRQ1 (7)
56 #define ODY_XCP_CM7_VEC_INT_E_EXT_INTX(a) (0x40 + (a))
57 #define ODY_XCP_CM7_VEC_INT_E_GIB0 (2)
58 #define ODY_XCP_CM7_VEC_INT_E_GIB1 (3)
59 #define ODY_XCP_CM7_VEC_INT_E_GIB2 (4)
60 #define ODY_XCP_CM7_VEC_INT_E_MBOX (5)
61 #define ODY_XCP_CM7_VEC_INT_E_RESERVEDX(a) (8 + (a))
62 #define ODY_XCP_CM7_VEC_INT_E_WDOG (1)
63
64 /**
65 * Enumeration xcp_dintf_err_type_e
66 *
67 * XCP Data Interface Precise Error Enumeration
68 * Enumerates the precise error types, as recorded in XCP()_PRECISE_BUS_ERR_STATUS[ERR_TYPE].
69 */
70 #define ODY_XCP_DINTF_ERR_TYPE_E_ACCESS_ERR (3)
71 #define ODY_XCP_DINTF_ERR_TYPE_E_ERR_NCB_CORE_RESET (5)
72 #define ODY_XCP_DINTF_ERR_TYPE_E_FETCH_ERR_NCB_FETCH_DIS (4)
73 #define ODY_XCP_DINTF_ERR_TYPE_E_INV_ADDR (2)
74 #define ODY_XCP_DINTF_ERR_TYPE_E_NO_ERR (0)
75 #define ODY_XCP_DINTF_ERR_TYPE_E_RD_ERR_NCB (6)
76 #define ODY_XCP_DINTF_ERR_TYPE_E_UMPD_ADDR (1)
77 #define ODY_XCP_DINTF_ERR_TYPE_E_WR_ERR_NCB (7)
78
79 /**
80 * Enumeration xcp_int_vec_e
81 *
82 * XCP MSI-X Vector Enumeration
83 * Enumerates the MSI-X interrupt vectors.
84 */
85 #define ODY_XCP_INT_VEC_E_XCP_DEV_MBOXX(a) (0 + (a))
86
87 /**
88 * Enumeration xcp_mbox_dev_e
89 *
90 * XCP Mailbox Device ID Enumeration
91 * Enumerates the device ID for MBOX registers.
92 */
93 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE0 (0x20)
94 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE1 (0x21)
95 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE10 (0x2a)
96 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE11 (0x2b)
97 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE12 (0x2c)
98 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE13 (0x2d)
99 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE14 (0x2e)
100 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE15 (0x2f)
101 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE16 (0x30)
102 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE17 (0x31)
103 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE18 (0x32)
104 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE19 (0x33)
105 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE2 (0x22)
106 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE20 (0x34)
107 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE21 (0x35)
108 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE22 (0x36)
109 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE23 (0x37)
110 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE3 (0x23)
111 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE4 (0x24)
112 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE5 (0x25)
113 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE6 (0x26)
114 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE7 (0x27)
115 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE8 (0x28)
116 #define ODY_XCP_MBOX_DEV_E_AP_NONSECURE9 (0x29)
117 #define ODY_XCP_MBOX_DEV_E_AP_SECURE0 (0)
118 #define ODY_XCP_MBOX_DEV_E_AP_SECURE1 (1)
119 #define ODY_XCP_MBOX_DEV_E_AP_SECURE10 (0xa)
120 #define ODY_XCP_MBOX_DEV_E_AP_SECURE11 (0xb)
121 #define ODY_XCP_MBOX_DEV_E_AP_SECURE12 (0xc)
122 #define ODY_XCP_MBOX_DEV_E_AP_SECURE13 (0xd)
123 #define ODY_XCP_MBOX_DEV_E_AP_SECURE14 (0xe)
124 #define ODY_XCP_MBOX_DEV_E_AP_SECURE15 (0xf)
125 #define ODY_XCP_MBOX_DEV_E_AP_SECURE16 (0x10)
126 #define ODY_XCP_MBOX_DEV_E_AP_SECURE17 (0x11)
127 #define ODY_XCP_MBOX_DEV_E_AP_SECURE18 (0x12)
128 #define ODY_XCP_MBOX_DEV_E_AP_SECURE19 (0x13)
129 #define ODY_XCP_MBOX_DEV_E_AP_SECURE2 (2)
130 #define ODY_XCP_MBOX_DEV_E_AP_SECURE20 (0x14)
131 #define ODY_XCP_MBOX_DEV_E_AP_SECURE21 (0x15)
132 #define ODY_XCP_MBOX_DEV_E_AP_SECURE22 (0x16)
133 #define ODY_XCP_MBOX_DEV_E_AP_SECURE23 (0x17)
134 #define ODY_XCP_MBOX_DEV_E_AP_SECURE24 (0x18)
135 #define ODY_XCP_MBOX_DEV_E_AP_SECURE25 (0x19)
136 #define ODY_XCP_MBOX_DEV_E_AP_SECURE26 (0x1a)
137 #define ODY_XCP_MBOX_DEV_E_AP_SECURE27 (0x1b)
138 #define ODY_XCP_MBOX_DEV_E_AP_SECURE28 (0x1c)
139 #define ODY_XCP_MBOX_DEV_E_AP_SECURE29 (0x1d)
140 #define ODY_XCP_MBOX_DEV_E_AP_SECURE3 (3)
141 #define ODY_XCP_MBOX_DEV_E_AP_SECURE30 (0x1e)
142 #define ODY_XCP_MBOX_DEV_E_AP_SECURE31 (0x1f)
143 #define ODY_XCP_MBOX_DEV_E_AP_SECURE4 (4)
144 #define ODY_XCP_MBOX_DEV_E_AP_SECURE5 (5)
145 #define ODY_XCP_MBOX_DEV_E_AP_SECURE6 (6)
146 #define ODY_XCP_MBOX_DEV_E_AP_SECURE7 (7)
147 #define ODY_XCP_MBOX_DEV_E_AP_SECURE8 (8)
148 #define ODY_XCP_MBOX_DEV_E_AP_SECURE9 (9)
149 #define ODY_XCP_MBOX_DEV_E_CCP_LOCAL (0x3a)
150 #define ODY_XCP_MBOX_DEV_E_CCP_REMOTE (0x3d)
151 #define ODY_XCP_MBOX_DEV_E_MCP_LOCAL (0x39)
152 #define ODY_XCP_MBOX_DEV_E_MCP_REMOTE (0x3c)
153 #define ODY_XCP_MBOX_DEV_E_SCP_LOCAL (0x38)
154 #define ODY_XCP_MBOX_DEV_E_SCP_REMOTE (0x3b)
155
156 /**
157 * Register (NCB) xcp#_anb_aximstr_status
158 *
159 * ANB AXISLV Block Status Register
160 * This register configures the connection XCP core and NCB.
161 */
162 union ody_xcpx_anb_aximstr_status {
163 uint64_t u;
164 struct ody_xcpx_anb_aximstr_status_s {
165 uint64_t anb_aximstr_rd_resp_nok : 1;
166 uint64_t anb_aximstr_wr_resp_nok : 1;
167 uint64_t reserved_2_63 : 62;
168 } s;
169 /* struct ody_xcpx_anb_aximstr_status_s cn; */
170 };
171 typedef union ody_xcpx_anb_aximstr_status ody_xcpx_anb_aximstr_status_t;
172
173 static inline uint64_t ODY_XCPX_ANB_AXIMSTR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_AXIMSTR_STATUS(uint64_t a)174 static inline uint64_t ODY_XCPX_ANB_AXIMSTR_STATUS(uint64_t a)
175 {
176 if (a <= 2)
177 return 0x82c000007060ll + 0x1000000000ll * ((a) & 0x3);
178 __ody_csr_fatal("XCPX_ANB_AXIMSTR_STATUS", 1, a, 0, 0, 0, 0, 0);
179 }
180
181 #define typedef_ODY_XCPX_ANB_AXIMSTR_STATUS(a) ody_xcpx_anb_aximstr_status_t
182 #define bustype_ODY_XCPX_ANB_AXIMSTR_STATUS(a) CSR_TYPE_NCB
183 #define basename_ODY_XCPX_ANB_AXIMSTR_STATUS(a) "XCPX_ANB_AXIMSTR_STATUS"
184 #define device_bar_ODY_XCPX_ANB_AXIMSTR_STATUS(a) 0x0 /* PF_BAR0 */
185 #define busnum_ODY_XCPX_ANB_AXIMSTR_STATUS(a) (a)
186 #define arguments_ODY_XCPX_ANB_AXIMSTR_STATUS(a) (a), -1, -1, -1
187
188 /**
189 * Register (NCB) xcp#_anb_axislv_status
190 *
191 * ANB AXISLV Block Status Register
192 * This register configures the connection XCP core and NCB.
193 */
194 union ody_xcpx_anb_axislv_status {
195 uint64_t u;
196 struct ody_xcpx_anb_axislv_status_s {
197 uint64_t anb_axislv_b_fifo_overrun : 1;
198 uint64_t anb_axislv_r_fifo_overrun : 1;
199 uint64_t anb_axislv_load_size_exc : 1;
200 uint64_t anb_axislv_write_size_exc : 1;
201 uint64_t anb_axislv_empty_write : 1;
202 uint64_t anb_axislv_multi_beat_nrw_wr : 1;
203 uint64_t anb_axislv_multi_beat_nrw_rd : 1;
204 uint64_t anb_axislv_single_beat_nrw_wr : 1;
205 uint64_t anb_axislv_single_beat_nrw_rd : 1;
206 uint64_t anb_axislv_bad_narrow_write_8 : 1;
207 uint64_t anb_axislv_bad_narrow_write_16 : 1;
208 uint64_t anb_axislv_bad_narrow_write_32 : 1;
209 uint64_t anb_axislv_bad_narrow_write_64 : 1;
210 uint64_t reserved_13_63 : 51;
211 } s;
212 /* struct ody_xcpx_anb_axislv_status_s cn; */
213 };
214 typedef union ody_xcpx_anb_axislv_status ody_xcpx_anb_axislv_status_t;
215
216 static inline uint64_t ODY_XCPX_ANB_AXISLV_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_AXISLV_STATUS(uint64_t a)217 static inline uint64_t ODY_XCPX_ANB_AXISLV_STATUS(uint64_t a)
218 {
219 if (a <= 2)
220 return 0x82c000007030ll + 0x1000000000ll * ((a) & 0x3);
221 __ody_csr_fatal("XCPX_ANB_AXISLV_STATUS", 1, a, 0, 0, 0, 0, 0);
222 }
223
224 #define typedef_ODY_XCPX_ANB_AXISLV_STATUS(a) ody_xcpx_anb_axislv_status_t
225 #define bustype_ODY_XCPX_ANB_AXISLV_STATUS(a) CSR_TYPE_NCB
226 #define basename_ODY_XCPX_ANB_AXISLV_STATUS(a) "XCPX_ANB_AXISLV_STATUS"
227 #define device_bar_ODY_XCPX_ANB_AXISLV_STATUS(a) 0x0 /* PF_BAR0 */
228 #define busnum_ODY_XCPX_ANB_AXISLV_STATUS(a) (a)
229 #define arguments_ODY_XCPX_ANB_AXISLV_STATUS(a) (a), -1, -1, -1
230
231 /**
232 * Register (NCB) xcp#_anb_backp_disable
233 *
234 * ANB Backpressure Configuration Register
235 * This register configures the connection XCP core and NCB.
236 */
237 union ody_xcpx_anb_backp_disable {
238 uint64_t u;
239 struct ody_xcpx_anb_backp_disable_s {
240 uint64_t anb_extmstr_b_backp_disable : 1;
241 uint64_t anb_extmstr_r_backp_disable : 1;
242 uint64_t anb_chicken_w_wait_for_aw : 1;
243 uint64_t anb_force_ncb_rst_active : 1;
244 uint64_t anb_ncb_rst_drain_axislv_fifos : 1;
245 uint64_t reserved_5_63 : 59;
246 } s;
247 /* struct ody_xcpx_anb_backp_disable_s cn; */
248 };
249 typedef union ody_xcpx_anb_backp_disable ody_xcpx_anb_backp_disable_t;
250
251 static inline uint64_t ODY_XCPX_ANB_BACKP_DISABLE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_BACKP_DISABLE(uint64_t a)252 static inline uint64_t ODY_XCPX_ANB_BACKP_DISABLE(uint64_t a)
253 {
254 if (a <= 2)
255 return 0x82c000007000ll + 0x1000000000ll * ((a) & 0x3);
256 __ody_csr_fatal("XCPX_ANB_BACKP_DISABLE", 1, a, 0, 0, 0, 0, 0);
257 }
258
259 #define typedef_ODY_XCPX_ANB_BACKP_DISABLE(a) ody_xcpx_anb_backp_disable_t
260 #define bustype_ODY_XCPX_ANB_BACKP_DISABLE(a) CSR_TYPE_NCB
261 #define basename_ODY_XCPX_ANB_BACKP_DISABLE(a) "XCPX_ANB_BACKP_DISABLE"
262 #define device_bar_ODY_XCPX_ANB_BACKP_DISABLE(a) 0x0 /* PF_BAR0 */
263 #define busnum_ODY_XCPX_ANB_BACKP_DISABLE(a) (a)
264 #define arguments_ODY_XCPX_ANB_BACKP_DISABLE(a) (a), -1, -1, -1
265
266 /**
267 * Register (NCB) xcp#_anb_ncbi_np_ovr
268 *
269 * ANB NCBITXT NP Path CMD Overrides Register
270 * This register configures the connection XCP core and NCB.
271 */
272 union ody_xcpx_anb_ncbi_np_ovr {
273 uint64_t u;
274 struct ody_xcpx_anb_ncbi_np_ovr_s {
275 uint64_t anb_ncbi_np_msh_dst_ovr_vld : 1;
276 uint64_t anb_ncbi_np_msh_dst_ovr : 11;
277 uint64_t anb_ncbi_np_ns_ovr_vld : 1;
278 uint64_t anb_ncbi_np_ns_ovr : 1;
279 uint64_t anb_ncbi_np_paddr_ovr_vld : 1;
280 uint64_t anb_ncbi_np_paddr_ovr : 1;
281 uint64_t anb_ncbi_np_ro_ovr_vld : 1;
282 uint64_t anb_ncbi_np_ro_ovr : 1;
283 uint64_t anb_ncbi_np_mpadid_val_ovr_vld : 1;
284 uint64_t anb_ncbi_np_mpadid_val_ovr : 1;
285 uint64_t anb_ncbi_np_mpamdid_ovr_vld : 1;
286 uint64_t anb_ncbi_np_mpamdid_ovr : 10;
287 uint64_t anb_ncbi_np_ldd_frc : 1;
288 uint64_t reserved_32_63 : 32;
289 } s;
290 /* struct ody_xcpx_anb_ncbi_np_ovr_s cn; */
291 };
292 typedef union ody_xcpx_anb_ncbi_np_ovr ody_xcpx_anb_ncbi_np_ovr_t;
293
294 static inline uint64_t ODY_XCPX_ANB_NCBI_NP_OVR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_NCBI_NP_OVR(uint64_t a)295 static inline uint64_t ODY_XCPX_ANB_NCBI_NP_OVR(uint64_t a)
296 {
297 if (a <= 2)
298 return 0x82c000007020ll + 0x1000000000ll * ((a) & 0x3);
299 __ody_csr_fatal("XCPX_ANB_NCBI_NP_OVR", 1, a, 0, 0, 0, 0, 0);
300 }
301
302 #define typedef_ODY_XCPX_ANB_NCBI_NP_OVR(a) ody_xcpx_anb_ncbi_np_ovr_t
303 #define bustype_ODY_XCPX_ANB_NCBI_NP_OVR(a) CSR_TYPE_NCB
304 #define basename_ODY_XCPX_ANB_NCBI_NP_OVR(a) "XCPX_ANB_NCBI_NP_OVR"
305 #define device_bar_ODY_XCPX_ANB_NCBI_NP_OVR(a) 0x0 /* PF_BAR0 */
306 #define busnum_ODY_XCPX_ANB_NCBI_NP_OVR(a) (a)
307 #define arguments_ODY_XCPX_ANB_NCBI_NP_OVR(a) (a), -1, -1, -1
308
309 /**
310 * Register (NCB) xcp#_anb_ncbi_p_ovr
311 *
312 * ANB NCBITXT P Overrides Register
313 * This register configures the connection XCP core and NCB.
314 */
315 union ody_xcpx_anb_ncbi_p_ovr {
316 uint64_t u;
317 struct ody_xcpx_anb_ncbi_p_ovr_s {
318 uint64_t anb_ncbi_p_msh_dst_ovr_vld : 1;
319 uint64_t anb_ncbi_p_msh_dst_ovr : 11;
320 uint64_t anb_ncbi_p_ns_ovr_vld : 1;
321 uint64_t anb_ncbi_p_ns_ovr : 1;
322 uint64_t anb_ncbi_p_paddr_ovr_vld : 1;
323 uint64_t anb_ncbi_p_paddr_ovr : 1;
324 uint64_t anb_ncbi_p_ro_ovr_vld : 1;
325 uint64_t anb_ncbi_p_ro_ovr : 1;
326 uint64_t anb_ncbi_p_mpadid_val_ovr_vld : 1;
327 uint64_t anb_ncbi_p_mpadid_val_ovr : 1;
328 uint64_t anb_ncbi_p_mpamdid_ovr_vld : 1;
329 uint64_t anb_ncbi_p_mpamdid_ovr : 10;
330 uint64_t anb_ncbi_p_stt_frc : 1;
331 uint64_t reserved_32_63 : 32;
332 } s;
333 /* struct ody_xcpx_anb_ncbi_p_ovr_s cn; */
334 };
335 typedef union ody_xcpx_anb_ncbi_p_ovr ody_xcpx_anb_ncbi_p_ovr_t;
336
337 static inline uint64_t ODY_XCPX_ANB_NCBI_P_OVR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_NCBI_P_OVR(uint64_t a)338 static inline uint64_t ODY_XCPX_ANB_NCBI_P_OVR(uint64_t a)
339 {
340 if (a <= 2)
341 return 0x82c000007010ll + 0x1000000000ll * ((a) & 0x3);
342 __ody_csr_fatal("XCPX_ANB_NCBI_P_OVR", 1, a, 0, 0, 0, 0, 0);
343 }
344
345 #define typedef_ODY_XCPX_ANB_NCBI_P_OVR(a) ody_xcpx_anb_ncbi_p_ovr_t
346 #define bustype_ODY_XCPX_ANB_NCBI_P_OVR(a) CSR_TYPE_NCB
347 #define basename_ODY_XCPX_ANB_NCBI_P_OVR(a) "XCPX_ANB_NCBI_P_OVR"
348 #define device_bar_ODY_XCPX_ANB_NCBI_P_OVR(a) 0x0 /* PF_BAR0 */
349 #define busnum_ODY_XCPX_ANB_NCBI_P_OVR(a) (a)
350 #define arguments_ODY_XCPX_ANB_NCBI_P_OVR(a) (a), -1, -1, -1
351
352 /**
353 * Register (NCB) xcp#_anb_ncbitx_status
354 *
355 * ANB AXISLV Block Status Register
356 * This register configures the connection XCP core and NCB.
357 */
358 union ody_xcpx_anb_ncbitx_status {
359 uint64_t u;
360 struct ody_xcpx_anb_ncbitx_status_s {
361 uint64_t anb_ncbitx_split_rd : 1;
362 uint64_t anb_ncbitx_split_wr : 1;
363 uint64_t reserved_2_63 : 62;
364 } s;
365 /* struct ody_xcpx_anb_ncbitx_status_s cn; */
366 };
367 typedef union ody_xcpx_anb_ncbitx_status ody_xcpx_anb_ncbitx_status_t;
368
369 static inline uint64_t ODY_XCPX_ANB_NCBITX_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_NCBITX_STATUS(uint64_t a)370 static inline uint64_t ODY_XCPX_ANB_NCBITX_STATUS(uint64_t a)
371 {
372 if (a <= 2)
373 return 0x82c000007040ll + 0x1000000000ll * ((a) & 0x3);
374 __ody_csr_fatal("XCPX_ANB_NCBITX_STATUS", 1, a, 0, 0, 0, 0, 0);
375 }
376
377 #define typedef_ODY_XCPX_ANB_NCBITX_STATUS(a) ody_xcpx_anb_ncbitx_status_t
378 #define bustype_ODY_XCPX_ANB_NCBITX_STATUS(a) CSR_TYPE_NCB
379 #define basename_ODY_XCPX_ANB_NCBITX_STATUS(a) "XCPX_ANB_NCBITX_STATUS"
380 #define device_bar_ODY_XCPX_ANB_NCBITX_STATUS(a) 0x0 /* PF_BAR0 */
381 #define busnum_ODY_XCPX_ANB_NCBITX_STATUS(a) (a)
382 #define arguments_ODY_XCPX_ANB_NCBITX_STATUS(a) (a), -1, -1, -1
383
384 /**
385 * Register (NCB) xcp#_anb_ncborx_status
386 *
387 * ANB AXISLV Block Status Register
388 * This register configures the connection XCP core and NCB.
389 */
390 union ody_xcpx_anb_ncborx_status {
391 uint64_t u;
392 struct ody_xcpx_anb_ncborx_status_s {
393 uint64_t anb_ncborx_rcvd_unsupported_op : 1;
394 uint64_t anb_nbcorx_max_num_ncb_ld_exc : 1;
395 uint64_t anb_nbcorx_max_size_ncb_ld_exc : 1;
396 uint64_t anb_nbcorx_max_num_ncb_st_exc : 1;
397 uint64_t anb_nbcorx_max_size_ncb_st_exc : 1;
398 uint64_t reserved_5_63 : 59;
399 } s;
400 /* struct ody_xcpx_anb_ncborx_status_s cn; */
401 };
402 typedef union ody_xcpx_anb_ncborx_status ody_xcpx_anb_ncborx_status_t;
403
404 static inline uint64_t ODY_XCPX_ANB_NCBORX_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ANB_NCBORX_STATUS(uint64_t a)405 static inline uint64_t ODY_XCPX_ANB_NCBORX_STATUS(uint64_t a)
406 {
407 if (a <= 2)
408 return 0x82c000007050ll + 0x1000000000ll * ((a) & 0x3);
409 __ody_csr_fatal("XCPX_ANB_NCBORX_STATUS", 1, a, 0, 0, 0, 0, 0);
410 }
411
412 #define typedef_ODY_XCPX_ANB_NCBORX_STATUS(a) ody_xcpx_anb_ncborx_status_t
413 #define bustype_ODY_XCPX_ANB_NCBORX_STATUS(a) CSR_TYPE_NCB
414 #define basename_ODY_XCPX_ANB_NCBORX_STATUS(a) "XCPX_ANB_NCBORX_STATUS"
415 #define device_bar_ODY_XCPX_ANB_NCBORX_STATUS(a) 0x0 /* PF_BAR0 */
416 #define busnum_ODY_XCPX_ANB_NCBORX_STATUS(a) (a)
417 #define arguments_ODY_XCPX_ANB_NCBORX_STATUS(a) (a), -1, -1, -1
418
419 /**
420 * Register (NCB32b) xcp#_boot_jump
421 *
422 * XCP Boot Jump Register
423 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
424 *
425 * This register is reset on chip reset.
426 */
427 union ody_xcpx_boot_jump {
428 uint32_t u;
429 struct ody_xcpx_boot_jump_s {
430 uint32_t addr : 32;
431 } s;
432 /* struct ody_xcpx_boot_jump_s cn; */
433 };
434 typedef union ody_xcpx_boot_jump ody_xcpx_boot_jump_t;
435
436 static inline uint64_t ODY_XCPX_BOOT_JUMP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_BOOT_JUMP(uint64_t a)437 static inline uint64_t ODY_XCPX_BOOT_JUMP(uint64_t a)
438 {
439 if (a <= 2)
440 return 0x82c000000130ll + 0x1000000000ll * ((a) & 0x3);
441 __ody_csr_fatal("XCPX_BOOT_JUMP", 1, a, 0, 0, 0, 0, 0);
442 }
443
444 #define typedef_ODY_XCPX_BOOT_JUMP(a) ody_xcpx_boot_jump_t
445 #define bustype_ODY_XCPX_BOOT_JUMP(a) CSR_TYPE_NCB32b
446 #define basename_ODY_XCPX_BOOT_JUMP(a) "XCPX_BOOT_JUMP"
447 #define device_bar_ODY_XCPX_BOOT_JUMP(a) 0x0 /* PF_BAR0 */
448 #define busnum_ODY_XCPX_BOOT_JUMP(a) (a)
449 #define arguments_ODY_XCPX_BOOT_JUMP(a) (a), -1, -1, -1
450
451 /**
452 * Register (NCB32b) xcp#_bus_err_lint
453 *
454 * XCP Bus error Interrupt Register
455 * This register assert error interrupt for XCP.
456 *
457 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
458 *
459 * This register is reset on XCP domain reset.
460 */
461 union ody_xcpx_bus_err_lint {
462 uint32_t u;
463 struct ody_xcpx_bus_err_lint_s {
464 uint32_t sw_bus_err : 1;
465 uint32_t reserved_1_31 : 31;
466 } s;
467 /* struct ody_xcpx_bus_err_lint_s cn; */
468 };
469 typedef union ody_xcpx_bus_err_lint ody_xcpx_bus_err_lint_t;
470
471 static inline uint64_t ODY_XCPX_BUS_ERR_LINT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_BUS_ERR_LINT(uint64_t a)472 static inline uint64_t ODY_XCPX_BUS_ERR_LINT(uint64_t a)
473 {
474 if (a <= 2)
475 return 0x82c000001c00ll + 0x1000000000ll * ((a) & 0x3);
476 __ody_csr_fatal("XCPX_BUS_ERR_LINT", 1, a, 0, 0, 0, 0, 0);
477 }
478
479 #define typedef_ODY_XCPX_BUS_ERR_LINT(a) ody_xcpx_bus_err_lint_t
480 #define bustype_ODY_XCPX_BUS_ERR_LINT(a) CSR_TYPE_NCB32b
481 #define basename_ODY_XCPX_BUS_ERR_LINT(a) "XCPX_BUS_ERR_LINT"
482 #define device_bar_ODY_XCPX_BUS_ERR_LINT(a) 0x0 /* PF_BAR0 */
483 #define busnum_ODY_XCPX_BUS_ERR_LINT(a) (a)
484 #define arguments_ODY_XCPX_BUS_ERR_LINT(a) (a), -1, -1, -1
485
486 /**
487 * Register (NCB32b) xcp#_bus_err_lint_ena_w1c
488 *
489 * XCP NCB bus error Interrupt Enable Clear Register
490 * This register clears interrupt enable bits.
491 */
492 union ody_xcpx_bus_err_lint_ena_w1c {
493 uint32_t u;
494 struct ody_xcpx_bus_err_lint_ena_w1c_s {
495 uint32_t sw_bus_err : 1;
496 uint32_t reserved_1_31 : 31;
497 } s;
498 /* struct ody_xcpx_bus_err_lint_ena_w1c_s cn; */
499 };
500 typedef union ody_xcpx_bus_err_lint_ena_w1c ody_xcpx_bus_err_lint_ena_w1c_t;
501
502 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_BUS_ERR_LINT_ENA_W1C(uint64_t a)503 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_ENA_W1C(uint64_t a)
504 {
505 if (a <= 2)
506 return 0x82c000001cc0ll + 0x1000000000ll * ((a) & 0x3);
507 __ody_csr_fatal("XCPX_BUS_ERR_LINT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
508 }
509
510 #define typedef_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) ody_xcpx_bus_err_lint_ena_w1c_t
511 #define bustype_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) CSR_TYPE_NCB32b
512 #define basename_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) "XCPX_BUS_ERR_LINT_ENA_W1C"
513 #define device_bar_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) 0x0 /* PF_BAR0 */
514 #define busnum_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) (a)
515 #define arguments_ODY_XCPX_BUS_ERR_LINT_ENA_W1C(a) (a), -1, -1, -1
516
517 /**
518 * Register (NCB32b) xcp#_bus_err_lint_ena_w1s
519 *
520 * XCP NCB bus error Interrupt Enable Set Register
521 * This register sets interrupt enable bits.
522 */
523 union ody_xcpx_bus_err_lint_ena_w1s {
524 uint32_t u;
525 struct ody_xcpx_bus_err_lint_ena_w1s_s {
526 uint32_t sw_bus_err : 1;
527 uint32_t reserved_1_31 : 31;
528 } s;
529 /* struct ody_xcpx_bus_err_lint_ena_w1s_s cn; */
530 };
531 typedef union ody_xcpx_bus_err_lint_ena_w1s ody_xcpx_bus_err_lint_ena_w1s_t;
532
533 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_BUS_ERR_LINT_ENA_W1S(uint64_t a)534 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_ENA_W1S(uint64_t a)
535 {
536 if (a <= 2)
537 return 0x82c000001ce0ll + 0x1000000000ll * ((a) & 0x3);
538 __ody_csr_fatal("XCPX_BUS_ERR_LINT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
539 }
540
541 #define typedef_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) ody_xcpx_bus_err_lint_ena_w1s_t
542 #define bustype_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) CSR_TYPE_NCB32b
543 #define basename_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) "XCPX_BUS_ERR_LINT_ENA_W1S"
544 #define device_bar_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) 0x0 /* PF_BAR0 */
545 #define busnum_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) (a)
546 #define arguments_ODY_XCPX_BUS_ERR_LINT_ENA_W1S(a) (a), -1, -1, -1
547
548 /**
549 * Register (NCB32b) xcp#_bus_err_lint_w1s
550 *
551 * XCP NCB bus error Interrupt Set Register
552 * This register sets interrupt bits.
553 */
554 union ody_xcpx_bus_err_lint_w1s {
555 uint32_t u;
556 struct ody_xcpx_bus_err_lint_w1s_s {
557 uint32_t sw_bus_err : 1;
558 uint32_t reserved_1_31 : 31;
559 } s;
560 /* struct ody_xcpx_bus_err_lint_w1s_s cn; */
561 };
562 typedef union ody_xcpx_bus_err_lint_w1s ody_xcpx_bus_err_lint_w1s_t;
563
564 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_BUS_ERR_LINT_W1S(uint64_t a)565 static inline uint64_t ODY_XCPX_BUS_ERR_LINT_W1S(uint64_t a)
566 {
567 if (a <= 2)
568 return 0x82c000001c80ll + 0x1000000000ll * ((a) & 0x3);
569 __ody_csr_fatal("XCPX_BUS_ERR_LINT_W1S", 1, a, 0, 0, 0, 0, 0);
570 }
571
572 #define typedef_ODY_XCPX_BUS_ERR_LINT_W1S(a) ody_xcpx_bus_err_lint_w1s_t
573 #define bustype_ODY_XCPX_BUS_ERR_LINT_W1S(a) CSR_TYPE_NCB32b
574 #define basename_ODY_XCPX_BUS_ERR_LINT_W1S(a) "XCPX_BUS_ERR_LINT_W1S"
575 #define device_bar_ODY_XCPX_BUS_ERR_LINT_W1S(a) 0x0 /* PF_BAR0 */
576 #define busnum_ODY_XCPX_BUS_ERR_LINT_W1S(a) (a)
577 #define arguments_ODY_XCPX_BUS_ERR_LINT_W1S(a) (a), -1, -1, -1
578
579 /**
580 * Register (NCB32b) xcp#_cfg
581 *
582 * XCP Configuration Register
583 * This register contains the configuration bits for XCP.
584 *
585 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
586 *
587 * This register is reset on XCP domain reset.
588 */
589 union ody_xcpx_cfg {
590 uint32_t u;
591 struct ody_xcpx_cfg_s {
592 uint32_t cfgbigend : 1;
593 uint32_t ext_fetch_dis : 1;
594 uint32_t reserved_2_7 : 6;
595 uint32_t ctlppblock : 4;
596 uint32_t chicken_ncb_b64 : 1;
597 uint32_t reserved_13_31 : 19;
598 } s;
599 /* struct ody_xcpx_cfg_s cn; */
600 };
601 typedef union ody_xcpx_cfg ody_xcpx_cfg_t;
602
603 static inline uint64_t ODY_XCPX_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CFG(uint64_t a)604 static inline uint64_t ODY_XCPX_CFG(uint64_t a)
605 {
606 if (a <= 2)
607 return 0x82c000000200ll + 0x1000000000ll * ((a) & 0x3);
608 __ody_csr_fatal("XCPX_CFG", 1, a, 0, 0, 0, 0, 0);
609 }
610
611 #define typedef_ODY_XCPX_CFG(a) ody_xcpx_cfg_t
612 #define bustype_ODY_XCPX_CFG(a) CSR_TYPE_NCB32b
613 #define basename_ODY_XCPX_CFG(a) "XCPX_CFG"
614 #define device_bar_ODY_XCPX_CFG(a) 0x0 /* PF_BAR0 */
615 #define busnum_ODY_XCPX_CFG(a) (a)
616 #define arguments_ODY_XCPX_CFG(a) (a), -1, -1, -1
617
618 /**
619 * Register (NCB32b) xcp#_clken
620 *
621 * XCP Clock Enable Register
622 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
623 *
624 * This register is reset on XCP domain reset.
625 */
626 union ody_xcpx_clken {
627 uint32_t u;
628 struct ody_xcpx_clken_s {
629 uint32_t clken : 1;
630 uint32_t reserved_1_31 : 31;
631 } s;
632 /* struct ody_xcpx_clken_s cn; */
633 };
634 typedef union ody_xcpx_clken ody_xcpx_clken_t;
635
636 static inline uint64_t ODY_XCPX_CLKEN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CLKEN(uint64_t a)637 static inline uint64_t ODY_XCPX_CLKEN(uint64_t a)
638 {
639 if (a <= 2)
640 return 0x82c000000010ll + 0x1000000000ll * ((a) & 0x3);
641 __ody_csr_fatal("XCPX_CLKEN", 1, a, 0, 0, 0, 0, 0);
642 }
643
644 #define typedef_ODY_XCPX_CLKEN(a) ody_xcpx_clken_t
645 #define bustype_ODY_XCPX_CLKEN(a) CSR_TYPE_NCB32b
646 #define basename_ODY_XCPX_CLKEN(a) "XCPX_CLKEN"
647 #define device_bar_ODY_XCPX_CLKEN(a) 0x0 /* PF_BAR0 */
648 #define busnum_ODY_XCPX_CLKEN(a) (a)
649 #define arguments_ODY_XCPX_CLKEN(a) (a), -1, -1, -1
650
651 /**
652 * Register (NCB32b) xcp#_cold_data
653 *
654 * XCP Cold Reset Data Register
655 * Opaque data preserved through XCP and warm resets. Reset on cold reset. This register is not
656 * reset on trusted-mode changes, so must not contain keys/secrets.
657 *
658 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
659 *
660 * This register is reset on cold reset.
661 */
662 union ody_xcpx_cold_data {
663 uint32_t u;
664 struct ody_xcpx_cold_data_s {
665 uint32_t data : 31;
666 uint32_t force_secondary : 1;
667 } s;
668 /* struct ody_xcpx_cold_data_s cn; */
669 };
670 typedef union ody_xcpx_cold_data ody_xcpx_cold_data_t;
671
672 static inline uint64_t ODY_XCPX_COLD_DATA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_COLD_DATA(uint64_t a)673 static inline uint64_t ODY_XCPX_COLD_DATA(uint64_t a)
674 {
675 if (a <= 2)
676 return 0x82c0000da000ll + 0x1000000000ll * ((a) & 0x3);
677 __ody_csr_fatal("XCPX_COLD_DATA", 1, a, 0, 0, 0, 0, 0);
678 }
679
680 #define typedef_ODY_XCPX_COLD_DATA(a) ody_xcpx_cold_data_t
681 #define bustype_ODY_XCPX_COLD_DATA(a) CSR_TYPE_NCB32b
682 #define basename_ODY_XCPX_COLD_DATA(a) "XCPX_COLD_DATA"
683 #define device_bar_ODY_XCPX_COLD_DATA(a) 0x0 /* PF_BAR0 */
684 #define busnum_ODY_XCPX_COLD_DATA(a) (a)
685 #define arguments_ODY_XCPX_COLD_DATA(a) (a), -1, -1, -1
686
687 /**
688 * Register (NCB32b) xcp#_cold_sticky_w1s
689 *
690 * XCP Cold Reset sticky W1S Register
691 * Opaque data preserved through XCP and warm resets. Writes of one stay as one until next cold
692 * reset; cannot write zeros. This register is not reset on trusted-mode changes, so must not
693 * contain keys/secrets.
694 *
695 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
696 *
697 * This register is reset on cold reset.
698 */
699 union ody_xcpx_cold_sticky_w1s {
700 uint32_t u;
701 struct ody_xcpx_cold_sticky_w1s_s {
702 uint32_t bl1_sz_inv : 6;
703 uint32_t data : 22;
704 uint32_t boot_rsvd : 2;
705 uint32_t boot_nsec : 1;
706 uint32_t boot_sec : 1;
707 } s;
708 /* struct ody_xcpx_cold_sticky_w1s_s cn; */
709 };
710 typedef union ody_xcpx_cold_sticky_w1s ody_xcpx_cold_sticky_w1s_t;
711
712 static inline uint64_t ODY_XCPX_COLD_STICKY_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_COLD_STICKY_W1S(uint64_t a)713 static inline uint64_t ODY_XCPX_COLD_STICKY_W1S(uint64_t a)
714 {
715 if (a <= 2)
716 return 0x82c0000da040ll + 0x1000000000ll * ((a) & 0x3);
717 __ody_csr_fatal("XCPX_COLD_STICKY_W1S", 1, a, 0, 0, 0, 0, 0);
718 }
719
720 #define typedef_ODY_XCPX_COLD_STICKY_W1S(a) ody_xcpx_cold_sticky_w1s_t
721 #define bustype_ODY_XCPX_COLD_STICKY_W1S(a) CSR_TYPE_NCB32b
722 #define basename_ODY_XCPX_COLD_STICKY_W1S(a) "XCPX_COLD_STICKY_W1S"
723 #define device_bar_ODY_XCPX_COLD_STICKY_W1S(a) 0x0 /* PF_BAR0 */
724 #define busnum_ODY_XCPX_COLD_STICKY_W1S(a) (a)
725 #define arguments_ODY_XCPX_COLD_STICKY_W1S(a) (a), -1, -1, -1
726
727 /**
728 * Register (NCB32b) xcp#_const
729 *
730 * XCP Constants Register
731 * This register is reset on XCP domain reset.
732 */
733 union ody_xcpx_const {
734 uint32_t u;
735 struct ody_xcpx_const_s {
736 uint32_t ncb_wins : 4;
737 uint32_t mrml_wins : 4;
738 uint32_t reserved_8_31 : 24;
739 } s;
740 /* struct ody_xcpx_const_s cn; */
741 };
742 typedef union ody_xcpx_const ody_xcpx_const_t;
743
744 static inline uint64_t ODY_XCPX_CONST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CONST(uint64_t a)745 static inline uint64_t ODY_XCPX_CONST(uint64_t a)
746 {
747 if (a <= 2)
748 return 0x82c000000000ll + 0x1000000000ll * ((a) & 0x3);
749 __ody_csr_fatal("XCPX_CONST", 1, a, 0, 0, 0, 0, 0);
750 }
751
752 #define typedef_ODY_XCPX_CONST(a) ody_xcpx_const_t
753 #define bustype_ODY_XCPX_CONST(a) CSR_TYPE_NCB32b
754 #define basename_ODY_XCPX_CONST(a) "XCPX_CONST"
755 #define device_bar_ODY_XCPX_CONST(a) 0x0 /* PF_BAR0 */
756 #define busnum_ODY_XCPX_CONST(a) (a)
757 #define arguments_ODY_XCPX_CONST(a) (a), -1, -1, -1
758
759 /**
760 * Register (NCB32b) xcp#_core_dcache_status
761 *
762 * XCP Core Data Cache Status Register
763 * This register contains sticky bits of XCP data cache error signaling.
764 *
765 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
766 *
767 * This register is reset on XCP domain reset.
768 */
769 union ody_xcpx_core_dcache_status {
770 uint32_t u;
771 struct ody_xcpx_core_dcache_status_s {
772 uint32_t dcerr : 22;
773 uint32_t reserved_22_23 : 2;
774 uint32_t dcdet : 4;
775 uint32_t reserved_28_31 : 4;
776 } s;
777 /* struct ody_xcpx_core_dcache_status_s cn; */
778 };
779 typedef union ody_xcpx_core_dcache_status ody_xcpx_core_dcache_status_t;
780
781 static inline uint64_t ODY_XCPX_CORE_DCACHE_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CORE_DCACHE_STATUS(uint64_t a)782 static inline uint64_t ODY_XCPX_CORE_DCACHE_STATUS(uint64_t a)
783 {
784 if (a <= 2)
785 return 0x82c000000180ll + 0x1000000000ll * ((a) & 0x3);
786 __ody_csr_fatal("XCPX_CORE_DCACHE_STATUS", 1, a, 0, 0, 0, 0, 0);
787 }
788
789 #define typedef_ODY_XCPX_CORE_DCACHE_STATUS(a) ody_xcpx_core_dcache_status_t
790 #define bustype_ODY_XCPX_CORE_DCACHE_STATUS(a) CSR_TYPE_NCB32b
791 #define basename_ODY_XCPX_CORE_DCACHE_STATUS(a) "XCPX_CORE_DCACHE_STATUS"
792 #define device_bar_ODY_XCPX_CORE_DCACHE_STATUS(a) 0x0 /* PF_BAR0 */
793 #define busnum_ODY_XCPX_CORE_DCACHE_STATUS(a) (a)
794 #define arguments_ODY_XCPX_CORE_DCACHE_STATUS(a) (a), -1, -1, -1
795
796 /**
797 * Register (NCB32b) xcp#_core_icache_status
798 *
799 * XCP Core Instruction Cache Status Register
800 * This register contains sticky bits of XCP instruction cache error signaling.
801 *
802 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
803 *
804 * This register is reset on XCP domain reset.
805 */
806 union ody_xcpx_core_icache_status {
807 uint32_t u;
808 struct ody_xcpx_core_icache_status_s {
809 uint32_t icerr : 22;
810 uint32_t reserved_22_23 : 2;
811 uint32_t icdet : 4;
812 uint32_t reserved_28_31 : 4;
813 } s;
814 /* struct ody_xcpx_core_icache_status_s cn; */
815 };
816 typedef union ody_xcpx_core_icache_status ody_xcpx_core_icache_status_t;
817
818 static inline uint64_t ODY_XCPX_CORE_ICACHE_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CORE_ICACHE_STATUS(uint64_t a)819 static inline uint64_t ODY_XCPX_CORE_ICACHE_STATUS(uint64_t a)
820 {
821 if (a <= 2)
822 return 0x82c000000190ll + 0x1000000000ll * ((a) & 0x3);
823 __ody_csr_fatal("XCPX_CORE_ICACHE_STATUS", 1, a, 0, 0, 0, 0, 0);
824 }
825
826 #define typedef_ODY_XCPX_CORE_ICACHE_STATUS(a) ody_xcpx_core_icache_status_t
827 #define bustype_ODY_XCPX_CORE_ICACHE_STATUS(a) CSR_TYPE_NCB32b
828 #define basename_ODY_XCPX_CORE_ICACHE_STATUS(a) "XCPX_CORE_ICACHE_STATUS"
829 #define device_bar_ODY_XCPX_CORE_ICACHE_STATUS(a) 0x0 /* PF_BAR0 */
830 #define busnum_ODY_XCPX_CORE_ICACHE_STATUS(a) (a)
831 #define arguments_ODY_XCPX_CORE_ICACHE_STATUS(a) (a), -1, -1, -1
832
833 /**
834 * Register (NCB32b) xcp#_cwd_lint
835 *
836 * XCP Per-core Watchdog Interrupt Register
837 * Generic timer per XCP watchdog interrupts.
838 *
839 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
840 *
841 * This register is reset on XCP domain reset.
842 */
843 union ody_xcpx_cwd_lint {
844 uint32_t u;
845 struct ody_xcpx_cwd_lint_s {
846 uint32_t wdog_int : 1;
847 uint32_t reserved_1_31 : 31;
848 } s;
849 /* struct ody_xcpx_cwd_lint_s cn; */
850 };
851 typedef union ody_xcpx_cwd_lint ody_xcpx_cwd_lint_t;
852
853 static inline uint64_t ODY_XCPX_CWD_LINT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_LINT(uint64_t a)854 static inline uint64_t ODY_XCPX_CWD_LINT(uint64_t a)
855 {
856 if (a <= 2)
857 return 0x82c000040200ll + 0x1000000000ll * ((a) & 0x3);
858 __ody_csr_fatal("XCPX_CWD_LINT", 1, a, 0, 0, 0, 0, 0);
859 }
860
861 #define typedef_ODY_XCPX_CWD_LINT(a) ody_xcpx_cwd_lint_t
862 #define bustype_ODY_XCPX_CWD_LINT(a) CSR_TYPE_NCB32b
863 #define basename_ODY_XCPX_CWD_LINT(a) "XCPX_CWD_LINT"
864 #define device_bar_ODY_XCPX_CWD_LINT(a) 0x0 /* PF_BAR0 */
865 #define busnum_ODY_XCPX_CWD_LINT(a) (a)
866 #define arguments_ODY_XCPX_CWD_LINT(a) (a), -1, -1, -1
867
868 /**
869 * Register (NCB32b) xcp#_cwd_lint_ena_w1c
870 *
871 * XCP Per-core Watchdog Interrupt Enable Clear Register
872 * This register clears interrupt enable bits.
873 */
874 union ody_xcpx_cwd_lint_ena_w1c {
875 uint32_t u;
876 struct ody_xcpx_cwd_lint_ena_w1c_s {
877 uint32_t wdog_int : 1;
878 uint32_t reserved_1_31 : 31;
879 } s;
880 /* struct ody_xcpx_cwd_lint_ena_w1c_s cn; */
881 };
882 typedef union ody_xcpx_cwd_lint_ena_w1c ody_xcpx_cwd_lint_ena_w1c_t;
883
884 static inline uint64_t ODY_XCPX_CWD_LINT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_LINT_ENA_W1C(uint64_t a)885 static inline uint64_t ODY_XCPX_CWD_LINT_ENA_W1C(uint64_t a)
886 {
887 if (a <= 2)
888 return 0x82c000040210ll + 0x1000000000ll * ((a) & 0x3);
889 __ody_csr_fatal("XCPX_CWD_LINT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
890 }
891
892 #define typedef_ODY_XCPX_CWD_LINT_ENA_W1C(a) ody_xcpx_cwd_lint_ena_w1c_t
893 #define bustype_ODY_XCPX_CWD_LINT_ENA_W1C(a) CSR_TYPE_NCB32b
894 #define basename_ODY_XCPX_CWD_LINT_ENA_W1C(a) "XCPX_CWD_LINT_ENA_W1C"
895 #define device_bar_ODY_XCPX_CWD_LINT_ENA_W1C(a) 0x0 /* PF_BAR0 */
896 #define busnum_ODY_XCPX_CWD_LINT_ENA_W1C(a) (a)
897 #define arguments_ODY_XCPX_CWD_LINT_ENA_W1C(a) (a), -1, -1, -1
898
899 /**
900 * Register (NCB32b) xcp#_cwd_lint_ena_w1s
901 *
902 * XCP Per-core Watchdog Interrupt Enable Set Register
903 * This register sets interrupt enable bits.
904 */
905 union ody_xcpx_cwd_lint_ena_w1s {
906 uint32_t u;
907 struct ody_xcpx_cwd_lint_ena_w1s_s {
908 uint32_t wdog_int : 1;
909 uint32_t reserved_1_31 : 31;
910 } s;
911 /* struct ody_xcpx_cwd_lint_ena_w1s_s cn; */
912 };
913 typedef union ody_xcpx_cwd_lint_ena_w1s ody_xcpx_cwd_lint_ena_w1s_t;
914
915 static inline uint64_t ODY_XCPX_CWD_LINT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_LINT_ENA_W1S(uint64_t a)916 static inline uint64_t ODY_XCPX_CWD_LINT_ENA_W1S(uint64_t a)
917 {
918 if (a <= 2)
919 return 0x82c000040218ll + 0x1000000000ll * ((a) & 0x3);
920 __ody_csr_fatal("XCPX_CWD_LINT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
921 }
922
923 #define typedef_ODY_XCPX_CWD_LINT_ENA_W1S(a) ody_xcpx_cwd_lint_ena_w1s_t
924 #define bustype_ODY_XCPX_CWD_LINT_ENA_W1S(a) CSR_TYPE_NCB32b
925 #define basename_ODY_XCPX_CWD_LINT_ENA_W1S(a) "XCPX_CWD_LINT_ENA_W1S"
926 #define device_bar_ODY_XCPX_CWD_LINT_ENA_W1S(a) 0x0 /* PF_BAR0 */
927 #define busnum_ODY_XCPX_CWD_LINT_ENA_W1S(a) (a)
928 #define arguments_ODY_XCPX_CWD_LINT_ENA_W1S(a) (a), -1, -1, -1
929
930 /**
931 * Register (NCB32b) xcp#_cwd_lint_w1s
932 *
933 * XCP Per-core Watchdog Interrupt Set Register
934 * This register sets interrupt bits.
935 */
936 union ody_xcpx_cwd_lint_w1s {
937 uint32_t u;
938 struct ody_xcpx_cwd_lint_w1s_s {
939 uint32_t wdog_int : 1;
940 uint32_t reserved_1_31 : 31;
941 } s;
942 /* struct ody_xcpx_cwd_lint_w1s_s cn; */
943 };
944 typedef union ody_xcpx_cwd_lint_w1s ody_xcpx_cwd_lint_w1s_t;
945
946 static inline uint64_t ODY_XCPX_CWD_LINT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_LINT_W1S(uint64_t a)947 static inline uint64_t ODY_XCPX_CWD_LINT_W1S(uint64_t a)
948 {
949 if (a <= 2)
950 return 0x82c000040208ll + 0x1000000000ll * ((a) & 0x3);
951 __ody_csr_fatal("XCPX_CWD_LINT_W1S", 1, a, 0, 0, 0, 0, 0);
952 }
953
954 #define typedef_ODY_XCPX_CWD_LINT_W1S(a) ody_xcpx_cwd_lint_w1s_t
955 #define bustype_ODY_XCPX_CWD_LINT_W1S(a) CSR_TYPE_NCB32b
956 #define basename_ODY_XCPX_CWD_LINT_W1S(a) "XCPX_CWD_LINT_W1S"
957 #define device_bar_ODY_XCPX_CWD_LINT_W1S(a) 0x0 /* PF_BAR0 */
958 #define busnum_ODY_XCPX_CWD_LINT_W1S(a) (a)
959 #define arguments_ODY_XCPX_CWD_LINT_W1S(a) (a), -1, -1, -1
960
961 /**
962 * Register (NCB32b) xcp#_cwd_nm_lint
963 *
964 * XCP Per-core Watchdog non-maskable Interrupt Register
965 * Generic timer per XCP watchdog non-maskable interrupts.
966 *
967 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
968 *
969 * This register is reset on XCP domain reset.
970 */
971 union ody_xcpx_cwd_nm_lint {
972 uint32_t u;
973 struct ody_xcpx_cwd_nm_lint_s {
974 uint32_t wdog_int : 1;
975 uint32_t reserved_1_31 : 31;
976 } s;
977 /* struct ody_xcpx_cwd_nm_lint_s cn; */
978 };
979 typedef union ody_xcpx_cwd_nm_lint ody_xcpx_cwd_nm_lint_t;
980
981 static inline uint64_t ODY_XCPX_CWD_NM_LINT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_NM_LINT(uint64_t a)982 static inline uint64_t ODY_XCPX_CWD_NM_LINT(uint64_t a)
983 {
984 if (a <= 2)
985 return 0x82c000041200ll + 0x1000000000ll * ((a) & 0x3);
986 __ody_csr_fatal("XCPX_CWD_NM_LINT", 1, a, 0, 0, 0, 0, 0);
987 }
988
989 #define typedef_ODY_XCPX_CWD_NM_LINT(a) ody_xcpx_cwd_nm_lint_t
990 #define bustype_ODY_XCPX_CWD_NM_LINT(a) CSR_TYPE_NCB32b
991 #define basename_ODY_XCPX_CWD_NM_LINT(a) "XCPX_CWD_NM_LINT"
992 #define device_bar_ODY_XCPX_CWD_NM_LINT(a) 0x0 /* PF_BAR0 */
993 #define busnum_ODY_XCPX_CWD_NM_LINT(a) (a)
994 #define arguments_ODY_XCPX_CWD_NM_LINT(a) (a), -1, -1, -1
995
996 /**
997 * Register (NCB32b) xcp#_cwd_nm_lint_w1s
998 *
999 * XCP Per-core Watchdog non-maskable Interrupt Set Register
1000 * This register sets interrupt bits.
1001 */
1002 union ody_xcpx_cwd_nm_lint_w1s {
1003 uint32_t u;
1004 struct ody_xcpx_cwd_nm_lint_w1s_s {
1005 uint32_t wdog_int : 1;
1006 uint32_t reserved_1_31 : 31;
1007 } s;
1008 /* struct ody_xcpx_cwd_nm_lint_w1s_s cn; */
1009 };
1010 typedef union ody_xcpx_cwd_nm_lint_w1s ody_xcpx_cwd_nm_lint_w1s_t;
1011
1012 static inline uint64_t ODY_XCPX_CWD_NM_LINT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_NM_LINT_W1S(uint64_t a)1013 static inline uint64_t ODY_XCPX_CWD_NM_LINT_W1S(uint64_t a)
1014 {
1015 if (a <= 2)
1016 return 0x82c000041208ll + 0x1000000000ll * ((a) & 0x3);
1017 __ody_csr_fatal("XCPX_CWD_NM_LINT_W1S", 1, a, 0, 0, 0, 0, 0);
1018 }
1019
1020 #define typedef_ODY_XCPX_CWD_NM_LINT_W1S(a) ody_xcpx_cwd_nm_lint_w1s_t
1021 #define bustype_ODY_XCPX_CWD_NM_LINT_W1S(a) CSR_TYPE_NCB32b
1022 #define basename_ODY_XCPX_CWD_NM_LINT_W1S(a) "XCPX_CWD_NM_LINT_W1S"
1023 #define device_bar_ODY_XCPX_CWD_NM_LINT_W1S(a) 0x0 /* PF_BAR0 */
1024 #define busnum_ODY_XCPX_CWD_NM_LINT_W1S(a) (a)
1025 #define arguments_ODY_XCPX_CWD_NM_LINT_W1S(a) (a), -1, -1, -1
1026
1027 /**
1028 * Register (NCB32b) xcp#_cwd_poke
1029 *
1030 * XCP Per-XCP Watchdog Poke Registers
1031 * Per-core watchdog poke. Writing any value to this register does the following:
1032 * * Clears any pending interrupt generated by the associated watchdog.
1033 * * Resets XCP()_CWD_WDOG[STATE] to 0x0.
1034 * * Sets XCP()_CWD_WDOG[CNT] to (XCP()_CWD_WDOG[LEN] \<\< 8)..
1035 *
1036 * Reading this register returns the associated XCP()_CWD_WDOG register.
1037 *
1038 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1039 *
1040 * This register is reset on XCP domain reset.
1041 */
1042 union ody_xcpx_cwd_poke {
1043 uint32_t u;
1044 struct ody_xcpx_cwd_poke_s {
1045 uint32_t ign : 32;
1046 } s;
1047 /* struct ody_xcpx_cwd_poke_s cn; */
1048 };
1049 typedef union ody_xcpx_cwd_poke ody_xcpx_cwd_poke_t;
1050
1051 static inline uint64_t ODY_XCPX_CWD_POKE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_POKE(uint64_t a)1052 static inline uint64_t ODY_XCPX_CWD_POKE(uint64_t a)
1053 {
1054 if (a <= 2)
1055 return 0x82c00000ee00ll + 0x1000000000ll * ((a) & 0x3);
1056 __ody_csr_fatal("XCPX_CWD_POKE", 1, a, 0, 0, 0, 0, 0);
1057 }
1058
1059 #define typedef_ODY_XCPX_CWD_POKE(a) ody_xcpx_cwd_poke_t
1060 #define bustype_ODY_XCPX_CWD_POKE(a) CSR_TYPE_NCB32b
1061 #define basename_ODY_XCPX_CWD_POKE(a) "XCPX_CWD_POKE"
1062 #define device_bar_ODY_XCPX_CWD_POKE(a) 0x0 /* PF_BAR0 */
1063 #define busnum_ODY_XCPX_CWD_POKE(a) (a)
1064 #define arguments_ODY_XCPX_CWD_POKE(a) (a), -1, -1, -1
1065
1066 /**
1067 * Register (NCB32b) xcp#_cwd_wdog
1068 *
1069 * XCP Per-XCP Watchdog Registers
1070 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1071 *
1072 * This register is reset on XCP domain reset.
1073 */
1074 union ody_xcpx_cwd_wdog {
1075 uint32_t u;
1076 struct ody_xcpx_cwd_wdog_s {
1077 uint32_t mode : 2;
1078 uint32_t state : 2;
1079 uint32_t len : 9;
1080 uint32_t cnt : 17;
1081 uint32_t dstop : 1;
1082 uint32_t gstop : 1;
1083 } s;
1084 /* struct ody_xcpx_cwd_wdog_s cn; */
1085 };
1086 typedef union ody_xcpx_cwd_wdog ody_xcpx_cwd_wdog_t;
1087
1088 static inline uint64_t ODY_XCPX_CWD_WDOG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_CWD_WDOG(uint64_t a)1089 static inline uint64_t ODY_XCPX_CWD_WDOG(uint64_t a)
1090 {
1091 if (a <= 2)
1092 return 0x82c00000ee80ll + 0x1000000000ll * ((a) & 0x3);
1093 __ody_csr_fatal("XCPX_CWD_WDOG", 1, a, 0, 0, 0, 0, 0);
1094 }
1095
1096 #define typedef_ODY_XCPX_CWD_WDOG(a) ody_xcpx_cwd_wdog_t
1097 #define bustype_ODY_XCPX_CWD_WDOG(a) CSR_TYPE_NCB32b
1098 #define basename_ODY_XCPX_CWD_WDOG(a) "XCPX_CWD_WDOG"
1099 #define device_bar_ODY_XCPX_CWD_WDOG(a) 0x0 /* PF_BAR0 */
1100 #define busnum_ODY_XCPX_CWD_WDOG(a) (a)
1101 #define arguments_ODY_XCPX_CWD_WDOG(a) (a), -1, -1, -1
1102
1103 /**
1104 * Register (NCB32b) xcp#_dev#_xcp_mbox
1105 *
1106 * XCP DEV-to-XCP Mailbox Data Registers
1107 * This register is the mailbox register for other devices to interrupt XCP
1108 * See XCP_MBOX_DEV_E for device enumeration.
1109 * For XCP-to-AP interrupts see instead XCP()_XCP_DEV()_MBOX.
1110 *
1111 * This register is only accessible to device driving this mailbox reg and the requestor(s)
1112 * permitted with CPC_XCP()_PERMIT.
1113 *
1114 * This register is reset on XCP domain reset.
1115 */
1116 union ody_xcpx_devx_xcp_mbox {
1117 uint32_t u;
1118 struct ody_xcpx_devx_xcp_mbox_s {
1119 uint32_t data : 32;
1120 } s;
1121 /* struct ody_xcpx_devx_xcp_mbox_s cn; */
1122 };
1123 typedef union ody_xcpx_devx_xcp_mbox ody_xcpx_devx_xcp_mbox_t;
1124
1125 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_DEVX_XCP_MBOX(uint64_t a,uint64_t b)1126 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX(uint64_t a, uint64_t b)
1127 {
1128 if ((a <= 2) && (b <= 61))
1129 return 0x82c0000e1000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1130 __ody_csr_fatal("XCPX_DEVX_XCP_MBOX", 2, a, b, 0, 0, 0, 0);
1131 }
1132
1133 #define typedef_ODY_XCPX_DEVX_XCP_MBOX(a, b) ody_xcpx_devx_xcp_mbox_t
1134 #define bustype_ODY_XCPX_DEVX_XCP_MBOX(a, b) CSR_TYPE_NCB32b
1135 #define basename_ODY_XCPX_DEVX_XCP_MBOX(a, b) "XCPX_DEVX_XCP_MBOX"
1136 #define device_bar_ODY_XCPX_DEVX_XCP_MBOX(a, b) 0x0 /* PF_BAR0 */
1137 #define busnum_ODY_XCPX_DEVX_XCP_MBOX(a, b) (a)
1138 #define arguments_ODY_XCPX_DEVX_XCP_MBOX(a, b) (a), (b), -1, -1
1139
1140 /**
1141 * Register (NCB32b) xcp#_dev#_xcp_mbox_lint
1142 *
1143 * XCP DEV-to-XCP Mailbox Interrupt Register
1144 * This register contains mailbox interrupt for Devs to XCP core transactions.
1145 *
1146 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1147 *
1148 * This register is reset on XCP domain reset.
1149 */
1150 union ody_xcpx_devx_xcp_mbox_lint {
1151 uint32_t u;
1152 struct ody_xcpx_devx_xcp_mbox_lint_s {
1153 uint32_t intr : 1;
1154 uint32_t reserved_1_31 : 31;
1155 } s;
1156 /* struct ody_xcpx_devx_xcp_mbox_lint_s cn; */
1157 };
1158 typedef union ody_xcpx_devx_xcp_mbox_lint ody_xcpx_devx_xcp_mbox_lint_t;
1159
1160 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_DEVX_XCP_MBOX_LINT(uint64_t a,uint64_t b)1161 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT(uint64_t a, uint64_t b)
1162 {
1163 if ((a <= 2) && (b <= 61))
1164 return 0x82c0000e2000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1165 __ody_csr_fatal("XCPX_DEVX_XCP_MBOX_LINT", 2, a, b, 0, 0, 0, 0);
1166 }
1167
1168 #define typedef_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) ody_xcpx_devx_xcp_mbox_lint_t
1169 #define bustype_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) CSR_TYPE_NCB32b
1170 #define basename_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) "XCPX_DEVX_XCP_MBOX_LINT"
1171 #define device_bar_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) 0x0 /* PF_BAR0 */
1172 #define busnum_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) (a)
1173 #define arguments_ODY_XCPX_DEVX_XCP_MBOX_LINT(a, b) (a), (b), -1, -1
1174
1175 /**
1176 * Register (NCB32b) xcp#_dev#_xcp_mbox_lint_ena_w1c
1177 *
1178 * XCP DEV-to-XCP Mailbox Interrupt Enable Clear Register
1179 * This register clears interrupt enable bits.
1180 */
1181 union ody_xcpx_devx_xcp_mbox_lint_ena_w1c {
1182 uint32_t u;
1183 struct ody_xcpx_devx_xcp_mbox_lint_ena_w1c_s {
1184 uint32_t intr : 1;
1185 uint32_t reserved_1_31 : 31;
1186 } s;
1187 /* struct ody_xcpx_devx_xcp_mbox_lint_ena_w1c_s cn; */
1188 };
1189 typedef union ody_xcpx_devx_xcp_mbox_lint_ena_w1c ody_xcpx_devx_xcp_mbox_lint_ena_w1c_t;
1190
1191 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(uint64_t a,uint64_t b)1192 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(uint64_t a, uint64_t b)
1193 {
1194 if ((a <= 2) && (b <= 61))
1195 return 0x82c0000e2c00ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1196 __ody_csr_fatal("XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C", 2, a, b, 0, 0, 0, 0);
1197 }
1198
1199 #define typedef_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) ody_xcpx_devx_xcp_mbox_lint_ena_w1c_t
1200 #define bustype_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) CSR_TYPE_NCB32b
1201 #define basename_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) "XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C"
1202 #define device_bar_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) 0x0 /* PF_BAR0 */
1203 #define busnum_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) (a)
1204 #define arguments_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1C(a, b) (a), (b), -1, -1
1205
1206 /**
1207 * Register (NCB32b) xcp#_dev#_xcp_mbox_lint_ena_w1s
1208 *
1209 * XCP DEV-to-XCP Mailbox Interrupt Enable Set Register
1210 * This register sets interrupt enable bits.
1211 */
1212 union ody_xcpx_devx_xcp_mbox_lint_ena_w1s {
1213 uint32_t u;
1214 struct ody_xcpx_devx_xcp_mbox_lint_ena_w1s_s {
1215 uint32_t intr : 1;
1216 uint32_t reserved_1_31 : 31;
1217 } s;
1218 /* struct ody_xcpx_devx_xcp_mbox_lint_ena_w1s_s cn; */
1219 };
1220 typedef union ody_xcpx_devx_xcp_mbox_lint_ena_w1s ody_xcpx_devx_xcp_mbox_lint_ena_w1s_t;
1221
1222 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(uint64_t a,uint64_t b)1223 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(uint64_t a, uint64_t b)
1224 {
1225 if ((a <= 2) && (b <= 61))
1226 return 0x82c0000e2800ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1227 __ody_csr_fatal("XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S", 2, a, b, 0, 0, 0, 0);
1228 }
1229
1230 #define typedef_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) ody_xcpx_devx_xcp_mbox_lint_ena_w1s_t
1231 #define bustype_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) CSR_TYPE_NCB32b
1232 #define basename_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) "XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S"
1233 #define device_bar_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) 0x0 /* PF_BAR0 */
1234 #define busnum_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) (a)
1235 #define arguments_ODY_XCPX_DEVX_XCP_MBOX_LINT_ENA_W1S(a, b) (a), (b), -1, -1
1236
1237 /**
1238 * Register (NCB32b) xcp#_dev#_xcp_mbox_lint_w1s
1239 *
1240 * XCP AP-to-XCP Mailbox Interrupt Set Register
1241 * This register sets interrupt bits.
1242 */
1243 union ody_xcpx_devx_xcp_mbox_lint_w1s {
1244 uint32_t u;
1245 struct ody_xcpx_devx_xcp_mbox_lint_w1s_s {
1246 uint32_t intr : 1;
1247 uint32_t reserved_1_31 : 31;
1248 } s;
1249 /* struct ody_xcpx_devx_xcp_mbox_lint_w1s_s cn; */
1250 };
1251 typedef union ody_xcpx_devx_xcp_mbox_lint_w1s ody_xcpx_devx_xcp_mbox_lint_w1s_t;
1252
1253 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(uint64_t a,uint64_t b)1254 static inline uint64_t ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(uint64_t a, uint64_t b)
1255 {
1256 if ((a <= 2) && (b <= 61))
1257 return 0x82c0000e2400ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1258 __ody_csr_fatal("XCPX_DEVX_XCP_MBOX_LINT_W1S", 2, a, b, 0, 0, 0, 0);
1259 }
1260
1261 #define typedef_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) ody_xcpx_devx_xcp_mbox_lint_w1s_t
1262 #define bustype_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) CSR_TYPE_NCB32b
1263 #define basename_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) "XCPX_DEVX_XCP_MBOX_LINT_W1S"
1264 #define device_bar_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) 0x0 /* PF_BAR0 */
1265 #define busnum_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) (a)
1266 #define arguments_ODY_XCPX_DEVX_XCP_MBOX_LINT_W1S(a, b) (a), (b), -1, -1
1267
1268 /**
1269 * Register (NCB32b) xcp#_gib#_lint
1270 *
1271 * XCP GIB Interrupt Register
1272 * This register contains GIB interrupt for XCP.
1273 *
1274 * This register and XCP()_GIB()_LINT_W1S are only accessible to the requestor(s)
1275 * permitted with CPC_XCP()_GIB()_LINT_PERMIT, or by a MSI-X/GIB interrupt message write.
1276 *
1277 * This register is reset on XCP domain reset.
1278 */
1279 union ody_xcpx_gibx_lint {
1280 uint32_t u;
1281 struct ody_xcpx_gibx_lint_s {
1282 uint32_t gib_int : 32;
1283 } s;
1284 /* struct ody_xcpx_gibx_lint_s cn; */
1285 };
1286 typedef union ody_xcpx_gibx_lint ody_xcpx_gibx_lint_t;
1287
1288 static inline uint64_t ODY_XCPX_GIBX_LINT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_GIBX_LINT(uint64_t a,uint64_t b)1289 static inline uint64_t ODY_XCPX_GIBX_LINT(uint64_t a, uint64_t b)
1290 {
1291 if ((a <= 2) && (b <= 2))
1292 return 0x82c000000c00ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1293 __ody_csr_fatal("XCPX_GIBX_LINT", 2, a, b, 0, 0, 0, 0);
1294 }
1295
1296 #define typedef_ODY_XCPX_GIBX_LINT(a, b) ody_xcpx_gibx_lint_t
1297 #define bustype_ODY_XCPX_GIBX_LINT(a, b) CSR_TYPE_NCB32b
1298 #define basename_ODY_XCPX_GIBX_LINT(a, b) "XCPX_GIBX_LINT"
1299 #define device_bar_ODY_XCPX_GIBX_LINT(a, b) 0x0 /* PF_BAR0 */
1300 #define busnum_ODY_XCPX_GIBX_LINT(a, b) (a)
1301 #define arguments_ODY_XCPX_GIBX_LINT(a, b) (a), (b), -1, -1
1302
1303 /**
1304 * Register (NCB32b) xcp#_gib#_lint_devid
1305 *
1306 * XCP GIB Interrupt Device ID Register
1307 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1308 *
1309 * This register is reset on XCP domain reset.
1310 */
1311 union ody_xcpx_gibx_lint_devid {
1312 uint32_t u;
1313 struct ody_xcpx_gibx_lint_devid_s {
1314 uint32_t devid : 22;
1315 uint32_t reserved_22_29 : 8;
1316 uint32_t ovfl : 1;
1317 uint32_t valid : 1;
1318 } s;
1319 /* struct ody_xcpx_gibx_lint_devid_s cn; */
1320 };
1321 typedef union ody_xcpx_gibx_lint_devid ody_xcpx_gibx_lint_devid_t;
1322
1323 static inline uint64_t ODY_XCPX_GIBX_LINT_DEVID(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_GIBX_LINT_DEVID(uint64_t a,uint64_t b)1324 static inline uint64_t ODY_XCPX_GIBX_LINT_DEVID(uint64_t a, uint64_t b)
1325 {
1326 if ((a <= 2) && (b <= 2))
1327 return 0x82c000000dc0ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1328 __ody_csr_fatal("XCPX_GIBX_LINT_DEVID", 2, a, b, 0, 0, 0, 0);
1329 }
1330
1331 #define typedef_ODY_XCPX_GIBX_LINT_DEVID(a, b) ody_xcpx_gibx_lint_devid_t
1332 #define bustype_ODY_XCPX_GIBX_LINT_DEVID(a, b) CSR_TYPE_NCB32b
1333 #define basename_ODY_XCPX_GIBX_LINT_DEVID(a, b) "XCPX_GIBX_LINT_DEVID"
1334 #define device_bar_ODY_XCPX_GIBX_LINT_DEVID(a, b) 0x0 /* PF_BAR0 */
1335 #define busnum_ODY_XCPX_GIBX_LINT_DEVID(a, b) (a)
1336 #define arguments_ODY_XCPX_GIBX_LINT_DEVID(a, b) (a), (b), -1, -1
1337
1338 /**
1339 * Register (NCB32b) xcp#_gib#_lint_ena_w1c
1340 *
1341 * XCP GIB Interrupt Enable Clear Register
1342 * This register clears interrupt enable bits.
1343 */
1344 union ody_xcpx_gibx_lint_ena_w1c {
1345 uint32_t u;
1346 struct ody_xcpx_gibx_lint_ena_w1c_s {
1347 uint32_t gib_int : 32;
1348 } s;
1349 /* struct ody_xcpx_gibx_lint_ena_w1c_s cn; */
1350 };
1351 typedef union ody_xcpx_gibx_lint_ena_w1c ody_xcpx_gibx_lint_ena_w1c_t;
1352
1353 static inline uint64_t ODY_XCPX_GIBX_LINT_ENA_W1C(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_GIBX_LINT_ENA_W1C(uint64_t a,uint64_t b)1354 static inline uint64_t ODY_XCPX_GIBX_LINT_ENA_W1C(uint64_t a, uint64_t b)
1355 {
1356 if ((a <= 2) && (b <= 2))
1357 return 0x82c000000cc0ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1358 __ody_csr_fatal("XCPX_GIBX_LINT_ENA_W1C", 2, a, b, 0, 0, 0, 0);
1359 }
1360
1361 #define typedef_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) ody_xcpx_gibx_lint_ena_w1c_t
1362 #define bustype_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) CSR_TYPE_NCB32b
1363 #define basename_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) "XCPX_GIBX_LINT_ENA_W1C"
1364 #define device_bar_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) 0x0 /* PF_BAR0 */
1365 #define busnum_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) (a)
1366 #define arguments_ODY_XCPX_GIBX_LINT_ENA_W1C(a, b) (a), (b), -1, -1
1367
1368 /**
1369 * Register (NCB32b) xcp#_gib#_lint_ena_w1s
1370 *
1371 * XCP GIB Interrupt Enable Set Register
1372 * This register sets interrupt enable bits.
1373 */
1374 union ody_xcpx_gibx_lint_ena_w1s {
1375 uint32_t u;
1376 struct ody_xcpx_gibx_lint_ena_w1s_s {
1377 uint32_t gib_int : 32;
1378 } s;
1379 /* struct ody_xcpx_gibx_lint_ena_w1s_s cn; */
1380 };
1381 typedef union ody_xcpx_gibx_lint_ena_w1s ody_xcpx_gibx_lint_ena_w1s_t;
1382
1383 static inline uint64_t ODY_XCPX_GIBX_LINT_ENA_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_GIBX_LINT_ENA_W1S(uint64_t a,uint64_t b)1384 static inline uint64_t ODY_XCPX_GIBX_LINT_ENA_W1S(uint64_t a, uint64_t b)
1385 {
1386 if ((a <= 2) && (b <= 2))
1387 return 0x82c000000c40ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1388 __ody_csr_fatal("XCPX_GIBX_LINT_ENA_W1S", 2, a, b, 0, 0, 0, 0);
1389 }
1390
1391 #define typedef_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) ody_xcpx_gibx_lint_ena_w1s_t
1392 #define bustype_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) CSR_TYPE_NCB32b
1393 #define basename_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) "XCPX_GIBX_LINT_ENA_W1S"
1394 #define device_bar_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) 0x0 /* PF_BAR0 */
1395 #define busnum_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) (a)
1396 #define arguments_ODY_XCPX_GIBX_LINT_ENA_W1S(a, b) (a), (b), -1, -1
1397
1398 /**
1399 * Register (NCB32b) xcp#_gib#_lint_w1s
1400 *
1401 * XCP GIB Interrupt Set Register
1402 * This register sets interrupt bits.
1403 */
1404 union ody_xcpx_gibx_lint_w1s {
1405 uint32_t u;
1406 struct ody_xcpx_gibx_lint_w1s_s {
1407 uint32_t gib_int : 32;
1408 } s;
1409 /* struct ody_xcpx_gibx_lint_w1s_s cn; */
1410 };
1411 typedef union ody_xcpx_gibx_lint_w1s ody_xcpx_gibx_lint_w1s_t;
1412
1413 static inline uint64_t ODY_XCPX_GIBX_LINT_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_GIBX_LINT_W1S(uint64_t a,uint64_t b)1414 static inline uint64_t ODY_XCPX_GIBX_LINT_W1S(uint64_t a, uint64_t b)
1415 {
1416 if ((a <= 2) && (b <= 2))
1417 return 0x82c000000c80ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1418 __ody_csr_fatal("XCPX_GIBX_LINT_W1S", 2, a, b, 0, 0, 0, 0);
1419 }
1420
1421 #define typedef_ODY_XCPX_GIBX_LINT_W1S(a, b) ody_xcpx_gibx_lint_w1s_t
1422 #define bustype_ODY_XCPX_GIBX_LINT_W1S(a, b) CSR_TYPE_NCB32b
1423 #define basename_ODY_XCPX_GIBX_LINT_W1S(a, b) "XCPX_GIBX_LINT_W1S"
1424 #define device_bar_ODY_XCPX_GIBX_LINT_W1S(a, b) 0x0 /* PF_BAR0 */
1425 #define busnum_ODY_XCPX_GIBX_LINT_W1S(a, b) (a)
1426 #define arguments_ODY_XCPX_GIBX_LINT_W1S(a, b) (a), (b), -1, -1
1427
1428 /**
1429 * Register (NCB32b) xcp#_id
1430 *
1431 * XCP Identefication Register
1432 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1433 *
1434 * This register is reset on XCP domain reset.
1435 */
1436 union ody_xcpx_id {
1437 uint32_t u;
1438 struct ody_xcpx_id_s {
1439 uint32_t id : 2;
1440 uint32_t reserved_2_31 : 30;
1441 } s;
1442 /* struct ody_xcpx_id_s cn; */
1443 };
1444 typedef union ody_xcpx_id ody_xcpx_id_t;
1445
1446 static inline uint64_t ODY_XCPX_ID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_ID(uint64_t a)1447 static inline uint64_t ODY_XCPX_ID(uint64_t a)
1448 {
1449 if (a <= 2)
1450 return 0x82c000000020ll + 0x1000000000ll * ((a) & 0x3);
1451 __ody_csr_fatal("XCPX_ID", 1, a, 0, 0, 0, 0, 0);
1452 }
1453
1454 #define typedef_ODY_XCPX_ID(a) ody_xcpx_id_t
1455 #define bustype_ODY_XCPX_ID(a) CSR_TYPE_NCB32b
1456 #define basename_ODY_XCPX_ID(a) "XCPX_ID"
1457 #define device_bar_ODY_XCPX_ID(a) 0x0 /* PF_BAR0 */
1458 #define busnum_ODY_XCPX_ID(a) (a)
1459 #define arguments_ODY_XCPX_ID(a) (a), -1, -1, -1
1460
1461 /**
1462 * Register (NCB32b) xcp#_initvtor
1463 *
1464 * XCP CM7 Init Vector Table Offeset Register
1465 * This register contains the configuration bits for the CM7 INITVTOR input port.
1466 *
1467 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1468 *
1469 * This register is reset on chip reset.
1470 */
1471 union ody_xcpx_initvtor {
1472 uint32_t u;
1473 struct ody_xcpx_initvtor_s {
1474 uint32_t reserved_0_6 : 7;
1475 uint32_t initvtor : 25;
1476 } s;
1477 /* struct ody_xcpx_initvtor_s cn; */
1478 };
1479 typedef union ody_xcpx_initvtor ody_xcpx_initvtor_t;
1480
1481 static inline uint64_t ODY_XCPX_INITVTOR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_INITVTOR(uint64_t a)1482 static inline uint64_t ODY_XCPX_INITVTOR(uint64_t a)
1483 {
1484 if (a <= 2)
1485 return 0x82c000000230ll + 0x1000000000ll * ((a) & 0x3);
1486 __ody_csr_fatal("XCPX_INITVTOR", 1, a, 0, 0, 0, 0, 0);
1487 }
1488
1489 #define typedef_ODY_XCPX_INITVTOR(a) ody_xcpx_initvtor_t
1490 #define bustype_ODY_XCPX_INITVTOR(a) CSR_TYPE_NCB32b
1491 #define basename_ODY_XCPX_INITVTOR(a) "XCPX_INITVTOR"
1492 #define device_bar_ODY_XCPX_INITVTOR(a) 0x0 /* PF_BAR0 */
1493 #define busnum_ODY_XCPX_INITVTOR(a) (a)
1494 #define arguments_ODY_XCPX_INITVTOR(a) (a), -1, -1, -1
1495
1496 /**
1497 * Register (NCB) xcp#_lint0_summary
1498 *
1499 * XCP Interrupt Summary Register 0
1500 * This register is the local interrupt summary register 0 for the XCP CPU core.
1501 *
1502 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1503 *
1504 * This register is reset on XCP domain reset.
1505 */
1506 union ody_xcpx_lint0_summary {
1507 uint64_t u;
1508 struct ody_xcpx_lint0_summary_s {
1509 uint64_t gib : 3;
1510 uint64_t reserved_3_14 : 12;
1511 uint64_t bus_err : 1;
1512 uint64_t reserved_16_17 : 2;
1513 uint64_t wdog_mi : 1;
1514 uint64_t wdog_nmi : 1;
1515 uint64_t reserved_20_63 : 44;
1516 } s;
1517 /* struct ody_xcpx_lint0_summary_s cn; */
1518 };
1519 typedef union ody_xcpx_lint0_summary ody_xcpx_lint0_summary_t;
1520
1521 static inline uint64_t ODY_XCPX_LINT0_SUMMARY(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_LINT0_SUMMARY(uint64_t a)1522 static inline uint64_t ODY_XCPX_LINT0_SUMMARY(uint64_t a)
1523 {
1524 if (a <= 2)
1525 return 0x82c0000e0000ll + 0x1000000000ll * ((a) & 0x3);
1526 __ody_csr_fatal("XCPX_LINT0_SUMMARY", 1, a, 0, 0, 0, 0, 0);
1527 }
1528
1529 #define typedef_ODY_XCPX_LINT0_SUMMARY(a) ody_xcpx_lint0_summary_t
1530 #define bustype_ODY_XCPX_LINT0_SUMMARY(a) CSR_TYPE_NCB
1531 #define basename_ODY_XCPX_LINT0_SUMMARY(a) "XCPX_LINT0_SUMMARY"
1532 #define device_bar_ODY_XCPX_LINT0_SUMMARY(a) 0x0 /* PF_BAR0 */
1533 #define busnum_ODY_XCPX_LINT0_SUMMARY(a) (a)
1534 #define arguments_ODY_XCPX_LINT0_SUMMARY(a) (a), -1, -1, -1
1535
1536 /**
1537 * Register (NCB) xcp#_lint1_summary
1538 *
1539 * XCP Interrupt Summary Register 1
1540 * This register is the local interrupt summary register 1 for the XCP CPU core.
1541 *
1542 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1543 *
1544 * This register is reset on XCP domain reset.
1545 */
1546 union ody_xcpx_lint1_summary {
1547 uint64_t u;
1548 struct ody_xcpx_lint1_summary_s {
1549 uint64_t mbox : 62;
1550 uint64_t reserved_62_63 : 2;
1551 } s;
1552 /* struct ody_xcpx_lint1_summary_s cn; */
1553 };
1554 typedef union ody_xcpx_lint1_summary ody_xcpx_lint1_summary_t;
1555
1556 static inline uint64_t ODY_XCPX_LINT1_SUMMARY(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_LINT1_SUMMARY(uint64_t a)1557 static inline uint64_t ODY_XCPX_LINT1_SUMMARY(uint64_t a)
1558 {
1559 if (a <= 2)
1560 return 0x82c0000e0008ll + 0x1000000000ll * ((a) & 0x3);
1561 __ody_csr_fatal("XCPX_LINT1_SUMMARY", 1, a, 0, 0, 0, 0, 0);
1562 }
1563
1564 #define typedef_ODY_XCPX_LINT1_SUMMARY(a) ody_xcpx_lint1_summary_t
1565 #define bustype_ODY_XCPX_LINT1_SUMMARY(a) CSR_TYPE_NCB
1566 #define basename_ODY_XCPX_LINT1_SUMMARY(a) "XCPX_LINT1_SUMMARY"
1567 #define device_bar_ODY_XCPX_LINT1_SUMMARY(a) 0x0 /* PF_BAR0 */
1568 #define busnum_ODY_XCPX_LINT1_SUMMARY(a) (a)
1569 #define arguments_ODY_XCPX_LINT1_SUMMARY(a) (a), -1, -1, -1
1570
1571 /**
1572 * Register (NCB32b) xcp#_mrml_64rd
1573 *
1574 * XCP MRML 64-bit Read Save/Restore Register
1575 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1576 *
1577 * This register is reset on XCP domain reset, and cannot be accessed during XCP domain reset.
1578 */
1579 union ody_xcpx_mrml_64rd {
1580 uint32_t u;
1581 struct ody_xcpx_mrml_64rd_s {
1582 uint32_t rd_data : 32;
1583 } s;
1584 /* struct ody_xcpx_mrml_64rd_s cn; */
1585 };
1586 typedef union ody_xcpx_mrml_64rd ody_xcpx_mrml_64rd_t;
1587
1588 static inline uint64_t ODY_XCPX_MRML_64RD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_MRML_64RD(uint64_t a)1589 static inline uint64_t ODY_XCPX_MRML_64RD(uint64_t a)
1590 {
1591 if (a <= 2)
1592 return 0x82c000000110ll + 0x1000000000ll * ((a) & 0x3);
1593 __ody_csr_fatal("XCPX_MRML_64RD", 1, a, 0, 0, 0, 0, 0);
1594 }
1595
1596 #define typedef_ODY_XCPX_MRML_64RD(a) ody_xcpx_mrml_64rd_t
1597 #define bustype_ODY_XCPX_MRML_64RD(a) CSR_TYPE_NCB32b
1598 #define basename_ODY_XCPX_MRML_64RD(a) "XCPX_MRML_64RD"
1599 #define device_bar_ODY_XCPX_MRML_64RD(a) 0x0 /* PF_BAR0 */
1600 #define busnum_ODY_XCPX_MRML_64RD(a) (a)
1601 #define arguments_ODY_XCPX_MRML_64RD(a) (a), -1, -1, -1
1602
1603 /**
1604 * Register (NCB32b) xcp#_mrml_64wr
1605 *
1606 * XCP MRML 64-bit Write Save/Restore Register
1607 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1608 *
1609 * This register is reset on XCP domain reset, and cannot be accessed during XCP domain reset.
1610 */
1611 union ody_xcpx_mrml_64wr {
1612 uint32_t u;
1613 struct ody_xcpx_mrml_64wr_s {
1614 uint32_t wr_data : 32;
1615 } s;
1616 /* struct ody_xcpx_mrml_64wr_s cn; */
1617 };
1618 typedef union ody_xcpx_mrml_64wr ody_xcpx_mrml_64wr_t;
1619
1620 static inline uint64_t ODY_XCPX_MRML_64WR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_MRML_64WR(uint64_t a)1621 static inline uint64_t ODY_XCPX_MRML_64WR(uint64_t a)
1622 {
1623 if (a <= 2)
1624 return 0x82c000000120ll + 0x1000000000ll * ((a) & 0x3);
1625 __ody_csr_fatal("XCPX_MRML_64WR", 1, a, 0, 0, 0, 0, 0);
1626 }
1627
1628 #define typedef_ODY_XCPX_MRML_64WR(a) ody_xcpx_mrml_64wr_t
1629 #define bustype_ODY_XCPX_MRML_64WR(a) CSR_TYPE_NCB32b
1630 #define basename_ODY_XCPX_MRML_64WR(a) "XCPX_MRML_64WR"
1631 #define device_bar_ODY_XCPX_MRML_64WR(a) 0x0 /* PF_BAR0 */
1632 #define busnum_ODY_XCPX_MRML_64WR(a) (a)
1633 #define arguments_ODY_XCPX_MRML_64WR(a) (a), -1, -1, -1
1634
1635 /**
1636 * Register (NCB32b) xcp#_mrml_win#_addr
1637 *
1638 * XCP RML Window Address Register
1639 * This register contains the upper address bits for the XCP core RML access windows.
1640 *
1641 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1642 *
1643 * This register is reset on XCP domain reset.
1644 */
1645 union ody_xcpx_mrml_winx_addr {
1646 uint32_t u;
1647 struct ody_xcpx_mrml_winx_addr_s {
1648 uint32_t addr : 24;
1649 uint32_t reserved_24_31 : 8;
1650 } s;
1651 /* struct ody_xcpx_mrml_winx_addr_s cn; */
1652 };
1653 typedef union ody_xcpx_mrml_winx_addr ody_xcpx_mrml_winx_addr_t;
1654
1655 static inline uint64_t ODY_XCPX_MRML_WINX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_MRML_WINX_ADDR(uint64_t a,uint64_t b)1656 static inline uint64_t ODY_XCPX_MRML_WINX_ADDR(uint64_t a, uint64_t b)
1657 {
1658 if ((a <= 2) && (b <= 3))
1659 return 0x82c000000800ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1660 __ody_csr_fatal("XCPX_MRML_WINX_ADDR", 2, a, b, 0, 0, 0, 0);
1661 }
1662
1663 #define typedef_ODY_XCPX_MRML_WINX_ADDR(a, b) ody_xcpx_mrml_winx_addr_t
1664 #define bustype_ODY_XCPX_MRML_WINX_ADDR(a, b) CSR_TYPE_NCB32b
1665 #define basename_ODY_XCPX_MRML_WINX_ADDR(a, b) "XCPX_MRML_WINX_ADDR"
1666 #define device_bar_ODY_XCPX_MRML_WINX_ADDR(a, b) 0x0 /* PF_BAR0 */
1667 #define busnum_ODY_XCPX_MRML_WINX_ADDR(a, b) (a)
1668 #define arguments_ODY_XCPX_MRML_WINX_ADDR(a, b) (a), (b), -1, -1
1669
1670 /**
1671 * Register (NCB32b) xcp#_mrml_win#_cfg
1672 *
1673 * XCP RML Window Configuration Register
1674 * This register contains the control bits for the XCP core RML access windows.
1675 *
1676 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1677 *
1678 * This register is reset on XCP domain reset.
1679 */
1680 union ody_xcpx_mrml_winx_cfg {
1681 uint32_t u;
1682 struct ody_xcpx_mrml_winx_cfg_s {
1683 uint32_t reserved_0_2 : 3;
1684 uint32_t secure : 2;
1685 uint32_t b64 : 1;
1686 uint32_t reserved_6_31 : 26;
1687 } s;
1688 /* struct ody_xcpx_mrml_winx_cfg_s cn; */
1689 };
1690 typedef union ody_xcpx_mrml_winx_cfg ody_xcpx_mrml_winx_cfg_t;
1691
1692 static inline uint64_t ODY_XCPX_MRML_WINX_CFG(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_MRML_WINX_CFG(uint64_t a,uint64_t b)1693 static inline uint64_t ODY_XCPX_MRML_WINX_CFG(uint64_t a, uint64_t b)
1694 {
1695 if ((a <= 2) && (b <= 3))
1696 return 0x82c000000700ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1697 __ody_csr_fatal("XCPX_MRML_WINX_CFG", 2, a, b, 0, 0, 0, 0);
1698 }
1699
1700 #define typedef_ODY_XCPX_MRML_WINX_CFG(a, b) ody_xcpx_mrml_winx_cfg_t
1701 #define bustype_ODY_XCPX_MRML_WINX_CFG(a, b) CSR_TYPE_NCB32b
1702 #define basename_ODY_XCPX_MRML_WINX_CFG(a, b) "XCPX_MRML_WINX_CFG"
1703 #define device_bar_ODY_XCPX_MRML_WINX_CFG(a, b) 0x0 /* PF_BAR0 */
1704 #define busnum_ODY_XCPX_MRML_WINX_CFG(a, b) (a)
1705 #define arguments_ODY_XCPX_MRML_WINX_CFG(a, b) (a), (b), -1, -1
1706
1707 /**
1708 * Register (NCB) xcp#_msix_pba#
1709 *
1710 * XCP MSI-X Pending Bit Array Registers
1711 * This register is the MSI-X PBA table; the bit number is indexed by the XCP_INT_VEC_E enumeration.
1712 *
1713 * This register is reset on chip reset.
1714 */
1715 union ody_xcpx_msix_pbax {
1716 uint64_t u;
1717 struct ody_xcpx_msix_pbax_s {
1718 uint64_t pend : 64;
1719 } s;
1720 /* struct ody_xcpx_msix_pbax_s cn; */
1721 };
1722 typedef union ody_xcpx_msix_pbax ody_xcpx_msix_pbax_t;
1723
1724 static inline uint64_t ODY_XCPX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_MSIX_PBAX(uint64_t a,uint64_t b)1725 static inline uint64_t ODY_XCPX_MSIX_PBAX(uint64_t a, uint64_t b)
1726 {
1727 if ((a <= 2) && (b == 0))
1728 return 0x82c0001f0000ll + 0x1000000000ll * ((a) & 0x3);
1729 __ody_csr_fatal("XCPX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0);
1730 }
1731
1732 #define typedef_ODY_XCPX_MSIX_PBAX(a, b) ody_xcpx_msix_pbax_t
1733 #define bustype_ODY_XCPX_MSIX_PBAX(a, b) CSR_TYPE_NCB
1734 #define basename_ODY_XCPX_MSIX_PBAX(a, b) "XCPX_MSIX_PBAX"
1735 #define device_bar_ODY_XCPX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */
1736 #define busnum_ODY_XCPX_MSIX_PBAX(a, b) (a)
1737 #define arguments_ODY_XCPX_MSIX_PBAX(a, b) (a), (b), -1, -1
1738
1739 /**
1740 * Register (NCB) xcp#_msix_vec#_addr
1741 *
1742 * XCP MSI-X Vector-Table Address Register
1743 * This register is the MSI-X vector table, indexed by the XCP_INT_VEC_E enumeration.
1744 *
1745 * This register is reset on chip reset.
1746 */
1747 union ody_xcpx_msix_vecx_addr {
1748 uint64_t u;
1749 struct ody_xcpx_msix_vecx_addr_s {
1750 uint64_t secvec : 1;
1751 uint64_t reserved_1 : 1;
1752 uint64_t addr : 51;
1753 uint64_t reserved_53_63 : 11;
1754 } s;
1755 /* struct ody_xcpx_msix_vecx_addr_s cn; */
1756 };
1757 typedef union ody_xcpx_msix_vecx_addr ody_xcpx_msix_vecx_addr_t;
1758
1759 static inline uint64_t ODY_XCPX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_MSIX_VECX_ADDR(uint64_t a,uint64_t b)1760 static inline uint64_t ODY_XCPX_MSIX_VECX_ADDR(uint64_t a, uint64_t b)
1761 {
1762 if ((a <= 2) && (b <= 55))
1763 return 0x82c000100000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1764 __ody_csr_fatal("XCPX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0);
1765 }
1766
1767 #define typedef_ODY_XCPX_MSIX_VECX_ADDR(a, b) ody_xcpx_msix_vecx_addr_t
1768 #define bustype_ODY_XCPX_MSIX_VECX_ADDR(a, b) CSR_TYPE_NCB
1769 #define basename_ODY_XCPX_MSIX_VECX_ADDR(a, b) "XCPX_MSIX_VECX_ADDR"
1770 #define device_bar_ODY_XCPX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */
1771 #define busnum_ODY_XCPX_MSIX_VECX_ADDR(a, b) (a)
1772 #define arguments_ODY_XCPX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1
1773
1774 /**
1775 * Register (NCB) xcp#_msix_vec#_ctl
1776 *
1777 * XCP MSI-X Vector-Table Control and Data Register
1778 * This register is the MSI-X vector table, indexed by the XCP_INT_VEC_E enumeration
1779 *
1780 * This register is reset on chip reset.
1781 */
1782 union ody_xcpx_msix_vecx_ctl {
1783 uint64_t u;
1784 struct ody_xcpx_msix_vecx_ctl_s {
1785 uint64_t data : 32;
1786 uint64_t mask : 1;
1787 uint64_t reserved_33_63 : 31;
1788 } s;
1789 /* struct ody_xcpx_msix_vecx_ctl_s cn; */
1790 };
1791 typedef union ody_xcpx_msix_vecx_ctl ody_xcpx_msix_vecx_ctl_t;
1792
1793 static inline uint64_t ODY_XCPX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_MSIX_VECX_CTL(uint64_t a,uint64_t b)1794 static inline uint64_t ODY_XCPX_MSIX_VECX_CTL(uint64_t a, uint64_t b)
1795 {
1796 if ((a <= 2) && (b <= 55))
1797 return 0x82c000100008ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
1798 __ody_csr_fatal("XCPX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0);
1799 }
1800
1801 #define typedef_ODY_XCPX_MSIX_VECX_CTL(a, b) ody_xcpx_msix_vecx_ctl_t
1802 #define bustype_ODY_XCPX_MSIX_VECX_CTL(a, b) CSR_TYPE_NCB
1803 #define basename_ODY_XCPX_MSIX_VECX_CTL(a, b) "XCPX_MSIX_VECX_CTL"
1804 #define device_bar_ODY_XCPX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */
1805 #define busnum_ODY_XCPX_MSIX_VECX_CTL(a, b) (a)
1806 #define arguments_ODY_XCPX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1
1807
1808 /**
1809 * Register (NCB32b) xcp#_ncb_64rd
1810 *
1811 * XCP NCB 64-bit Read Save/Restore Register
1812 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1813 *
1814 * This register is reset on XCP domain reset.
1815 */
1816 union ody_xcpx_ncb_64rd {
1817 uint32_t u;
1818 struct ody_xcpx_ncb_64rd_s {
1819 uint32_t rd_data : 32;
1820 } s;
1821 /* struct ody_xcpx_ncb_64rd_s cn; */
1822 };
1823 typedef union ody_xcpx_ncb_64rd ody_xcpx_ncb_64rd_t;
1824
1825 static inline uint64_t ODY_XCPX_NCB_64RD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_NCB_64RD(uint64_t a)1826 static inline uint64_t ODY_XCPX_NCB_64RD(uint64_t a)
1827 {
1828 if (a <= 2)
1829 return 0x82c000000140ll + 0x1000000000ll * ((a) & 0x3);
1830 __ody_csr_fatal("XCPX_NCB_64RD", 1, a, 0, 0, 0, 0, 0);
1831 }
1832
1833 #define typedef_ODY_XCPX_NCB_64RD(a) ody_xcpx_ncb_64rd_t
1834 #define bustype_ODY_XCPX_NCB_64RD(a) CSR_TYPE_NCB32b
1835 #define basename_ODY_XCPX_NCB_64RD(a) "XCPX_NCB_64RD"
1836 #define device_bar_ODY_XCPX_NCB_64RD(a) 0x0 /* PF_BAR0 */
1837 #define busnum_ODY_XCPX_NCB_64RD(a) (a)
1838 #define arguments_ODY_XCPX_NCB_64RD(a) (a), -1, -1, -1
1839
1840 /**
1841 * Register (NCB32b) xcp#_ncb_win#_addr
1842 *
1843 * XCP NCB Window Address Register
1844 * This register contains the upper address bits for the XCP core NCB access windows.
1845 *
1846 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1847 *
1848 * This register is reset on XCP domain reset.
1849 *
1850 * The windows should not have overlapping address spaces if caching is enabled.
1851 */
1852 union ody_xcpx_ncb_winx_addr {
1853 uint32_t u;
1854 struct ody_xcpx_ncb_winx_addr_s {
1855 uint32_t addr : 29;
1856 uint32_t reserved_29_31 : 3;
1857 } s;
1858 /* struct ody_xcpx_ncb_winx_addr_s cn; */
1859 };
1860 typedef union ody_xcpx_ncb_winx_addr ody_xcpx_ncb_winx_addr_t;
1861
1862 static inline uint64_t ODY_XCPX_NCB_WINX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_NCB_WINX_ADDR(uint64_t a,uint64_t b)1863 static inline uint64_t ODY_XCPX_NCB_WINX_ADDR(uint64_t a, uint64_t b)
1864 {
1865 if ((a <= 2) && (b <= 3))
1866 return 0x82c000000400ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1867 __ody_csr_fatal("XCPX_NCB_WINX_ADDR", 2, a, b, 0, 0, 0, 0);
1868 }
1869
1870 #define typedef_ODY_XCPX_NCB_WINX_ADDR(a, b) ody_xcpx_ncb_winx_addr_t
1871 #define bustype_ODY_XCPX_NCB_WINX_ADDR(a, b) CSR_TYPE_NCB32b
1872 #define basename_ODY_XCPX_NCB_WINX_ADDR(a, b) "XCPX_NCB_WINX_ADDR"
1873 #define device_bar_ODY_XCPX_NCB_WINX_ADDR(a, b) 0x0 /* PF_BAR0 */
1874 #define busnum_ODY_XCPX_NCB_WINX_ADDR(a, b) (a)
1875 #define arguments_ODY_XCPX_NCB_WINX_ADDR(a, b) (a), (b), -1, -1
1876
1877 /**
1878 * Register (NCB32b) xcp#_ncb_win#_cfg
1879 *
1880 * XCP NCB Window Configuration Register
1881 * This register contains the control bits for the XCP core NCB access windows.
1882 *
1883 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1884 *
1885 * This register is reset on XCP domain reset.
1886 */
1887 union ody_xcpx_ncb_winx_cfg {
1888 uint32_t u;
1889 struct ody_xcpx_ncb_winx_cfg_s {
1890 uint32_t cacheable : 2;
1891 uint32_t phys : 1;
1892 uint32_t secure : 2;
1893 uint32_t b64 : 1;
1894 uint32_t reserved_6_31 : 26;
1895 } s;
1896 /* struct ody_xcpx_ncb_winx_cfg_s cn; */
1897 };
1898 typedef union ody_xcpx_ncb_winx_cfg ody_xcpx_ncb_winx_cfg_t;
1899
1900 static inline uint64_t ODY_XCPX_NCB_WINX_CFG(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_NCB_WINX_CFG(uint64_t a,uint64_t b)1901 static inline uint64_t ODY_XCPX_NCB_WINX_CFG(uint64_t a, uint64_t b)
1902 {
1903 if ((a <= 2) && (b <= 3))
1904 return 0x82c000000300ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
1905 __ody_csr_fatal("XCPX_NCB_WINX_CFG", 2, a, b, 0, 0, 0, 0);
1906 }
1907
1908 #define typedef_ODY_XCPX_NCB_WINX_CFG(a, b) ody_xcpx_ncb_winx_cfg_t
1909 #define bustype_ODY_XCPX_NCB_WINX_CFG(a, b) CSR_TYPE_NCB32b
1910 #define basename_ODY_XCPX_NCB_WINX_CFG(a, b) "XCPX_NCB_WINX_CFG"
1911 #define device_bar_ODY_XCPX_NCB_WINX_CFG(a, b) 0x0 /* PF_BAR0 */
1912 #define busnum_ODY_XCPX_NCB_WINX_CFG(a, b) (a)
1913 #define arguments_ODY_XCPX_NCB_WINX_CFG(a, b) (a), (b), -1, -1
1914
1915 /**
1916 * Register (NCB32b) xcp#_precise_bus_err_addr
1917 *
1918 * XCP Precise Bus Error Address Register
1919 * This register contains the address of the precise data bus interface error for XCP.
1920 *
1921 * This register is reset on XCP domain reset.
1922 */
1923 union ody_xcpx_precise_bus_err_addr {
1924 uint32_t u;
1925 struct ody_xcpx_precise_bus_err_addr_s {
1926 uint32_t addr : 32;
1927 } s;
1928 /* struct ody_xcpx_precise_bus_err_addr_s cn; */
1929 };
1930 typedef union ody_xcpx_precise_bus_err_addr ody_xcpx_precise_bus_err_addr_t;
1931
1932 static inline uint64_t ODY_XCPX_PRECISE_BUS_ERR_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_PRECISE_BUS_ERR_ADDR(uint64_t a)1933 static inline uint64_t ODY_XCPX_PRECISE_BUS_ERR_ADDR(uint64_t a)
1934 {
1935 if (a <= 2)
1936 return 0x82c000001d00ll + 0x1000000000ll * ((a) & 0x3);
1937 __ody_csr_fatal("XCPX_PRECISE_BUS_ERR_ADDR", 1, a, 0, 0, 0, 0, 0);
1938 }
1939
1940 #define typedef_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) ody_xcpx_precise_bus_err_addr_t
1941 #define bustype_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) CSR_TYPE_NCB32b
1942 #define basename_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) "XCPX_PRECISE_BUS_ERR_ADDR"
1943 #define device_bar_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) 0x0 /* PF_BAR0 */
1944 #define busnum_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) (a)
1945 #define arguments_ODY_XCPX_PRECISE_BUS_ERR_ADDR(a) (a), -1, -1, -1
1946
1947 /**
1948 * Register (NCB32b) xcp#_precise_bus_err_status
1949 *
1950 * XCP Precise Bus Error Status Register
1951 * This register contains the state of the precise data bus interface error for XCP.
1952 *
1953 * This register is reset on XCP domain reset.
1954 */
1955 union ody_xcpx_precise_bus_err_status {
1956 uint32_t u;
1957 struct ody_xcpx_precise_bus_err_status_s {
1958 uint32_t part : 3;
1959 uint32_t err_type : 3;
1960 uint32_t val : 1;
1961 uint32_t reserved_7_31 : 25;
1962 } s;
1963 /* struct ody_xcpx_precise_bus_err_status_s cn; */
1964 };
1965 typedef union ody_xcpx_precise_bus_err_status ody_xcpx_precise_bus_err_status_t;
1966
1967 static inline uint64_t ODY_XCPX_PRECISE_BUS_ERR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_PRECISE_BUS_ERR_STATUS(uint64_t a)1968 static inline uint64_t ODY_XCPX_PRECISE_BUS_ERR_STATUS(uint64_t a)
1969 {
1970 if (a <= 2)
1971 return 0x82c000001d08ll + 0x1000000000ll * ((a) & 0x3);
1972 __ody_csr_fatal("XCPX_PRECISE_BUS_ERR_STATUS", 1, a, 0, 0, 0, 0, 0);
1973 }
1974
1975 #define typedef_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) ody_xcpx_precise_bus_err_status_t
1976 #define bustype_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) CSR_TYPE_NCB32b
1977 #define basename_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) "XCPX_PRECISE_BUS_ERR_STATUS"
1978 #define device_bar_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) 0x0 /* PF_BAR0 */
1979 #define busnum_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) (a)
1980 #define arguments_ODY_XCPX_PRECISE_BUS_ERR_STATUS(a) (a), -1, -1, -1
1981
1982 /**
1983 * Register (NCB32b) xcp#_ram_win#
1984 *
1985 * XCP RAM Window Register
1986 * This register contains the base address and size for the XCP core access windows to CPC RAM.
1987 *
1988 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
1989 *
1990 * This register is reset on XCP domain reset.
1991 */
1992 union ody_xcpx_ram_winx {
1993 uint32_t u;
1994 struct ody_xcpx_ram_winx_s {
1995 uint32_t base : 6;
1996 uint32_t reserved_6_7 : 2;
1997 uint32_t size : 6;
1998 uint32_t reserved_14_31 : 18;
1999 } s;
2000 /* struct ody_xcpx_ram_winx_s cn; */
2001 };
2002 typedef union ody_xcpx_ram_winx ody_xcpx_ram_winx_t;
2003
2004 static inline uint64_t ODY_XCPX_RAM_WINX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_RAM_WINX(uint64_t a,uint64_t b)2005 static inline uint64_t ODY_XCPX_RAM_WINX(uint64_t a, uint64_t b)
2006 {
2007 if ((a <= 2) && (b <= 3))
2008 return 0x82c000000600ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
2009 __ody_csr_fatal("XCPX_RAM_WINX", 2, a, b, 0, 0, 0, 0);
2010 }
2011
2012 #define typedef_ODY_XCPX_RAM_WINX(a, b) ody_xcpx_ram_winx_t
2013 #define bustype_ODY_XCPX_RAM_WINX(a, b) CSR_TYPE_NCB32b
2014 #define basename_ODY_XCPX_RAM_WINX(a, b) "XCPX_RAM_WINX"
2015 #define device_bar_ODY_XCPX_RAM_WINX(a, b) 0x0 /* PF_BAR0 */
2016 #define busnum_ODY_XCPX_RAM_WINX(a, b) (a)
2017 #define arguments_ODY_XCPX_RAM_WINX(a, b) (a), (b), -1, -1
2018
2019 /**
2020 * Register (NCB32b) xcp#_status
2021 *
2022 * XCP Status Register
2023 * This register contains the status bits for XCP.
2024 *
2025 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
2026 *
2027 * This register is reset on XCP domain reset.
2028 */
2029 union ody_xcpx_status {
2030 uint32_t u;
2031 struct ody_xcpx_status_s {
2032 uint32_t lock_up : 1;
2033 uint32_t wrap_err : 1;
2034 uint32_t reserved_2_31 : 30;
2035 } s;
2036 /* struct ody_xcpx_status_s cn; */
2037 };
2038 typedef union ody_xcpx_status ody_xcpx_status_t;
2039
2040 static inline uint64_t ODY_XCPX_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_STATUS(uint64_t a)2041 static inline uint64_t ODY_XCPX_STATUS(uint64_t a)
2042 {
2043 if (a <= 2)
2044 return 0x82c000000210ll + 0x1000000000ll * ((a) & 0x3);
2045 __ody_csr_fatal("XCPX_STATUS", 1, a, 0, 0, 0, 0, 0);
2046 }
2047
2048 #define typedef_ODY_XCPX_STATUS(a) ody_xcpx_status_t
2049 #define bustype_ODY_XCPX_STATUS(a) CSR_TYPE_NCB32b
2050 #define basename_ODY_XCPX_STATUS(a) "XCPX_STATUS"
2051 #define device_bar_ODY_XCPX_STATUS(a) 0x0 /* PF_BAR0 */
2052 #define busnum_ODY_XCPX_STATUS(a) (a)
2053 #define arguments_ODY_XCPX_STATUS(a) (a), -1, -1, -1
2054
2055 /**
2056 * Register (NCB32b) xcp#_stcalib
2057 *
2058 * XCP CM7 STCALIB Configuration Register
2059 * This register contains the configuration bits for the CM7 STCALIB input port.
2060 *
2061 * This register is only accessible to the requestor(s) permitted with CPC_XCP()_PERMIT.
2062 *
2063 * This register is reset on XCP domain reset.
2064 */
2065 union ody_xcpx_stcalib {
2066 uint32_t u;
2067 struct ody_xcpx_stcalib_s {
2068 uint32_t stcalib : 26;
2069 uint32_t reserved_26_31 : 6;
2070 } s;
2071 /* struct ody_xcpx_stcalib_s cn; */
2072 };
2073 typedef union ody_xcpx_stcalib ody_xcpx_stcalib_t;
2074
2075 static inline uint64_t ODY_XCPX_STCALIB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_XCPX_STCALIB(uint64_t a)2076 static inline uint64_t ODY_XCPX_STCALIB(uint64_t a)
2077 {
2078 if (a <= 2)
2079 return 0x82c000000240ll + 0x1000000000ll * ((a) & 0x3);
2080 __ody_csr_fatal("XCPX_STCALIB", 1, a, 0, 0, 0, 0, 0);
2081 }
2082
2083 #define typedef_ODY_XCPX_STCALIB(a) ody_xcpx_stcalib_t
2084 #define bustype_ODY_XCPX_STCALIB(a) CSR_TYPE_NCB32b
2085 #define basename_ODY_XCPX_STCALIB(a) "XCPX_STCALIB"
2086 #define device_bar_ODY_XCPX_STCALIB(a) 0x0 /* PF_BAR0 */
2087 #define busnum_ODY_XCPX_STCALIB(a) (a)
2088 #define arguments_ODY_XCPX_STCALIB(a) (a), -1, -1, -1
2089
2090 /**
2091 * Register (NCB32b) xcp#_xcp_dev#_mbox
2092 *
2093 * XCP XCP-to-AP Mailbox Data Registers
2094 * This register is the mailbox register for XCP-to-AP core transactions.
2095 * For AP-to-XCP and XCP-to-XCP interrupts see instead XCP()_DEV()_XCP_MBOX.
2096 *
2097 * This register is only accessible to the associated device (based on DEV index by
2098 * XCP_MBOX_DEV_E) and the requestor(s) permitted with CPC_XCP()_PERMIT.
2099 */
2100 union ody_xcpx_xcp_devx_mbox {
2101 uint32_t u;
2102 struct ody_xcpx_xcp_devx_mbox_s {
2103 uint32_t data : 32;
2104 } s;
2105 /* struct ody_xcpx_xcp_devx_mbox_s cn; */
2106 };
2107 typedef union ody_xcpx_xcp_devx_mbox ody_xcpx_xcp_devx_mbox_t;
2108
2109 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_XCP_DEVX_MBOX(uint64_t a,uint64_t b)2110 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX(uint64_t a, uint64_t b)
2111 {
2112 if ((a <= 2) && (b <= 55))
2113 return 0x82c0000d2000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
2114 __ody_csr_fatal("XCPX_XCP_DEVX_MBOX", 2, a, b, 0, 0, 0, 0);
2115 }
2116
2117 #define typedef_ODY_XCPX_XCP_DEVX_MBOX(a, b) ody_xcpx_xcp_devx_mbox_t
2118 #define bustype_ODY_XCPX_XCP_DEVX_MBOX(a, b) CSR_TYPE_NCB32b
2119 #define basename_ODY_XCPX_XCP_DEVX_MBOX(a, b) "XCPX_XCP_DEVX_MBOX"
2120 #define device_bar_ODY_XCPX_XCP_DEVX_MBOX(a, b) 0x0 /* PF_BAR0 */
2121 #define busnum_ODY_XCPX_XCP_DEVX_MBOX(a, b) (a)
2122 #define arguments_ODY_XCPX_XCP_DEVX_MBOX(a, b) (a), (b), -1, -1
2123
2124 /**
2125 * Register (NCB) xcp#_xcp_dev#_mbox_rint
2126 *
2127 * XCP XCP-to-AP Mailbox Interrupt Register
2128 * This register contains mailbox interrupt for XCP-to-AP core transactions.
2129 *
2130 * This register is only accessible to the associated device (based on DEV index by
2131 * XCP_MBOX_DEV_E) and the requestor(s) permitted with CPC_XCP()_PERMIT.
2132 *
2133 * This register is reset on XCP domain reset.
2134 */
2135 union ody_xcpx_xcp_devx_mbox_rint {
2136 uint64_t u;
2137 struct ody_xcpx_xcp_devx_mbox_rint_s {
2138 uint64_t intr : 1;
2139 uint64_t reserved_1_63 : 63;
2140 } s;
2141 /* struct ody_xcpx_xcp_devx_mbox_rint_s cn; */
2142 };
2143 typedef union ody_xcpx_xcp_devx_mbox_rint ody_xcpx_xcp_devx_mbox_rint_t;
2144
2145 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_XCP_DEVX_MBOX_RINT(uint64_t a,uint64_t b)2146 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT(uint64_t a, uint64_t b)
2147 {
2148 if ((a <= 2) && (b <= 55))
2149 return 0x82c0000d3000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
2150 __ody_csr_fatal("XCPX_XCP_DEVX_MBOX_RINT", 2, a, b, 0, 0, 0, 0);
2151 }
2152
2153 #define typedef_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) ody_xcpx_xcp_devx_mbox_rint_t
2154 #define bustype_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) CSR_TYPE_NCB
2155 #define basename_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) "XCPX_XCP_DEVX_MBOX_RINT"
2156 #define device_bar_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) 0x0 /* PF_BAR0 */
2157 #define busnum_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) (a)
2158 #define arguments_ODY_XCPX_XCP_DEVX_MBOX_RINT(a, b) (a), (b), -1, -1
2159
2160 /**
2161 * Register (NCB) xcp#_xcp_dev#_mbox_rint_ena_w1c
2162 *
2163 * XCP XCP-to-AP Mailbox Interrupt Enable Clear Register
2164 * This register clears interrupt enable bits.
2165 */
2166 union ody_xcpx_xcp_devx_mbox_rint_ena_w1c {
2167 uint64_t u;
2168 struct ody_xcpx_xcp_devx_mbox_rint_ena_w1c_s {
2169 uint64_t intr : 1;
2170 uint64_t reserved_1_63 : 63;
2171 } s;
2172 /* struct ody_xcpx_xcp_devx_mbox_rint_ena_w1c_s cn; */
2173 };
2174 typedef union ody_xcpx_xcp_devx_mbox_rint_ena_w1c ody_xcpx_xcp_devx_mbox_rint_ena_w1c_t;
2175
2176 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(uint64_t a,uint64_t b)2177 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(uint64_t a, uint64_t b)
2178 {
2179 if ((a <= 2) && (b <= 55))
2180 return 0x82c0000d3c00ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
2181 __ody_csr_fatal("XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C", 2, a, b, 0, 0, 0, 0);
2182 }
2183
2184 #define typedef_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) ody_xcpx_xcp_devx_mbox_rint_ena_w1c_t
2185 #define bustype_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) CSR_TYPE_NCB
2186 #define basename_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) "XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C"
2187 #define device_bar_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) 0x0 /* PF_BAR0 */
2188 #define busnum_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) (a)
2189 #define arguments_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1C(a, b) (a), (b), -1, -1
2190
2191 /**
2192 * Register (NCB) xcp#_xcp_dev#_mbox_rint_ena_w1s
2193 *
2194 * XCP XCP-to-AP Mailbox Interrupt Enable Set Register
2195 * This register sets interrupt enable bits.
2196 */
2197 union ody_xcpx_xcp_devx_mbox_rint_ena_w1s {
2198 uint64_t u;
2199 struct ody_xcpx_xcp_devx_mbox_rint_ena_w1s_s {
2200 uint64_t intr : 1;
2201 uint64_t reserved_1_63 : 63;
2202 } s;
2203 /* struct ody_xcpx_xcp_devx_mbox_rint_ena_w1s_s cn; */
2204 };
2205 typedef union ody_xcpx_xcp_devx_mbox_rint_ena_w1s ody_xcpx_xcp_devx_mbox_rint_ena_w1s_t;
2206
2207 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(uint64_t a,uint64_t b)2208 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(uint64_t a, uint64_t b)
2209 {
2210 if ((a <= 2) && (b <= 55))
2211 return 0x82c0000d3400ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
2212 __ody_csr_fatal("XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S", 2, a, b, 0, 0, 0, 0);
2213 }
2214
2215 #define typedef_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) ody_xcpx_xcp_devx_mbox_rint_ena_w1s_t
2216 #define bustype_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) CSR_TYPE_NCB
2217 #define basename_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) "XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S"
2218 #define device_bar_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) 0x0 /* PF_BAR0 */
2219 #define busnum_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) (a)
2220 #define arguments_ODY_XCPX_XCP_DEVX_MBOX_RINT_ENA_W1S(a, b) (a), (b), -1, -1
2221
2222 /**
2223 * Register (NCB) xcp#_xcp_dev#_mbox_rint_w1s
2224 *
2225 * XCP XCP-to-AP Mailbox Interrupt Set Register
2226 * This register sets interrupt bits.
2227 */
2228 union ody_xcpx_xcp_devx_mbox_rint_w1s {
2229 uint64_t u;
2230 struct ody_xcpx_xcp_devx_mbox_rint_w1s_s {
2231 uint64_t intr : 1;
2232 uint64_t reserved_1_63 : 63;
2233 } s;
2234 /* struct ody_xcpx_xcp_devx_mbox_rint_w1s_s cn; */
2235 };
2236 typedef union ody_xcpx_xcp_devx_mbox_rint_w1s ody_xcpx_xcp_devx_mbox_rint_w1s_t;
2237
2238 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(uint64_t a,uint64_t b)2239 static inline uint64_t ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(uint64_t a, uint64_t b)
2240 {
2241 if ((a <= 2) && (b <= 55))
2242 return 0x82c0000d3800ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3f);
2243 __ody_csr_fatal("XCPX_XCP_DEVX_MBOX_RINT_W1S", 2, a, b, 0, 0, 0, 0);
2244 }
2245
2246 #define typedef_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) ody_xcpx_xcp_devx_mbox_rint_w1s_t
2247 #define bustype_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) CSR_TYPE_NCB
2248 #define basename_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) "XCPX_XCP_DEVX_MBOX_RINT_W1S"
2249 #define device_bar_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) 0x0 /* PF_BAR0 */
2250 #define busnum_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) (a)
2251 #define arguments_ODY_XCPX_XCP_DEVX_MBOX_RINT_W1S(a, b) (a), (b), -1, -1
2252
2253 #endif /* __ODY_CSRS_XCP_H__ */
2254