1 /* 2 * Copyright (c) 2025-2026 Texas Instruments Incorporated - https://www.ti.com 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef TI_CLK_IDS_H 7 #define TI_CLK_IDS_H 8 9 #define CLK_AM62LX_RESERVED 0 10 #define CLK_AM62LX_GLUELOGIC_HFOSC0_CLK 1 11 #define CLK_AM62LX_GLUELOGIC_LFOSC0_CLK 2 12 #define CLK_AM62LX_GLUELOGIC_RCOSC_CLKOUT 3 13 #define CLK_AM62LX_GLUELOGIC_RCOSC_CLK_1P0V_97P65K 4 14 #define CLK_AM62LX_BOARD_0_AUDIO_EXT_REFCLK0_OUT 5 15 #define CLK_AM62LX_BOARD_0_AUDIO_EXT_REFCLK1_OUT 6 16 #define CLK_AM62LX_BOARD_0_GEMAC_CPTS0_RFT_CLK_OUT 7 17 #define CLK_AM62LX_BOARD_0_EXT_REFCLK1_OUT 8 18 #define CLK_AM62LX_BOARD_0_GPMC0_CLKLB_OUT 9 19 #define CLK_AM62LX_BOARD_0_I2C0_SCL_OUT 10 20 #define CLK_AM62LX_BOARD_0_I2C1_SCL_OUT 11 21 #define CLK_AM62LX_BOARD_0_I2C2_SCL_OUT 12 22 #define CLK_AM62LX_BOARD_0_I2C3_SCL_OUT 13 23 #define CLK_AM62LX_BOARD_0_MCASP0_ACLKR_OUT 14 24 #define CLK_AM62LX_BOARD_0_MCASP0_ACLKX_OUT 15 25 #define CLK_AM62LX_BOARD_0_MCASP0_AFSR_OUT 16 26 #define CLK_AM62LX_BOARD_0_MCASP0_AFSX_OUT 17 27 #define CLK_AM62LX_BOARD_0_MCASP1_ACLKR_OUT 18 28 #define CLK_AM62LX_BOARD_0_MCASP1_ACLKX_OUT 19 29 #define CLK_AM62LX_BOARD_0_MCASP1_AFSR_OUT 20 30 #define CLK_AM62LX_BOARD_0_MCASP1_AFSX_OUT 21 31 #define CLK_AM62LX_BOARD_0_MCASP2_ACLKR_OUT 22 32 #define CLK_AM62LX_BOARD_0_MCASP2_ACLKX_OUT 23 33 #define CLK_AM62LX_BOARD_0_MCASP2_AFSR_OUT 24 34 #define CLK_AM62LX_BOARD_0_MCASP2_AFSX_OUT 25 35 #define CLK_AM62LX_BOARD_0_MMC0_CLKLB_OUT 26 36 #define CLK_AM62LX_BOARD_0_MMC0_CLK_OUT 27 37 #define CLK_AM62LX_BOARD_0_MMC1_CLKLB_OUT 28 38 #define CLK_AM62LX_BOARD_0_MMC1_CLK_OUT 29 39 #define CLK_AM62LX_BOARD_0_MMC2_CLKLB_OUT 30 40 #define CLK_AM62LX_BOARD_0_MMC2_CLK_OUT 31 41 #define CLK_AM62LX_BOARD_0_OSPI0_DQS_OUT 32 42 #define CLK_AM62LX_BOARD_0_OSPI0_LBCLKO_OUT 33 43 #define CLK_AM62LX_BOARD_0_RMII1_REF_CLK_OUT 34 44 #define CLK_AM62LX_BOARD_0_RMII2_REF_CLK_OUT 35 45 #define CLK_AM62LX_BOARD_0_TCK_OUT 36 46 #define CLK_AM62LX_BOARD_0_VOUT0_EXTPCLKIN_OUT 37 47 #define CLK_AM62LX_BOARD_0_WKUP_EXT_REFCLK0_OUT 38 48 #define CLK_AM62LX_BOARD_0_WKUP_I2C0_SCL_OUT 39 49 #define CLK_AM62LX_CPSW_MAIN_0_CPTS_GENF0 40 50 #define CLK_AM62LX_CPSW_MAIN_0_CPTS_GENF1 41 51 #define CLK_AM62LX_CPSW_3GUSS_AM62L_MAIN_0_MDIO_MDCLK_O 42 52 #define CLK_AM62LX_DEBUGSS_K3_WRAP_CV0_MAIN_0_CSTPIU_TRACECLK 43 53 #define CLK_AM62LX_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 44 54 #define CLK_AM62LX_DMTIMER_DMC1MS_MAIN_1_TIMER_PWM 45 55 #define CLK_AM62LX_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 46 56 #define CLK_AM62LX_DMTIMER_DMC1MS_MAIN_3_TIMER_PWM 47 57 #define CLK_AM62LX_DMC1MS_WKUP_0_TIMER_PWM 48 58 #define CLK_AM62LX_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O 49 59 #define CLK_AM62LX_EMMCSD4SS_MAIN_1_EMMCSDSS_IO_CLK_O 50 60 #define CLK_AM62LX_EMMCSD8SS_MAIN_0_EMMCSDSS_IO_CLK_O 51 61 #define CLK_AM62LX_FSS_UL_128_MAIN_0_OSPI0_OCLK_CLK 52 62 #define CLK_AM62LX_GPMC_MAIN_0_PO_GPMC_DEV_CLK 53 63 #define CLK_AM62LX_HSDIV0_16FFT_WKUP_32KHZ_GEN_0_HSDIVOUT0_CLK 54 64 #define CLK_AM62LX_K3_DSS_NANO_MAIN_0_DPI_0_OUT_CLK 55 65 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_ACLKR_POUT 56 66 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_ACLKX_POUT 57 67 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_AFSR_POUT 58 68 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_AFSX_POUT 59 69 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_AHCLKR_POUT 60 70 #define CLK_AM62LX_MCASP_MAIN_0_MCASP_AHCLKX_POUT 61 71 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_ACLKR_POUT 62 72 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_ACLKX_POUT 63 73 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_AFSR_POUT 64 74 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_AFSX_POUT 65 75 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_AHCLKR_POUT 66 76 #define CLK_AM62LX_MCASP_MAIN_1_MCASP_AHCLKX_POUT 67 77 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_ACLKR_POUT 68 78 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_ACLKX_POUT 69 79 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_AFSR_POUT 70 80 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_AFSX_POUT 71 81 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_AHCLKR_POUT 72 82 #define CLK_AM62LX_MCASP_MAIN_2_MCASP_AHCLKX_POUT 73 83 #define CLK_AM62LX_MSHSI2C_MAIN_0_PORSCL 74 84 #define CLK_AM62LX_MSHSI2C_MAIN_1_PORSCL 75 85 #define CLK_AM62LX_MSHSI2C_MAIN_2_PORSCL 76 86 #define CLK_AM62LX_MSHSI2C_MAIN_3_PORSCL 77 87 #define CLK_AM62LX_MSHSI2C_WKUP_0_PORSCL 78 88 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_MAIN_0_FOUTVCOP_CLK 79 89 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_MAIN_0_FOUTPOSTDIV_CLK 80 90 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_MAIN_17_FOUTVCOP_CLK 81 91 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK 82 92 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_WKUP_0_FOUTVCOP_CLK 83 93 #define CLK_AM62LX_PLLFRACF2_SSMOD_16FFT_WKUP_0_FOUTPOSTDIV_CLK 84 94 #define CLK_AM62LX_POSTDIV4_MAIN_0_HSDIVOUT5_CLK 85 95 #define CLK_AM62LX_POSTDIV4_MAIN_0_HSDIVOUT6_CLK 86 96 #define CLK_AM62LX_POSTDIV4_MAIN_0_HSDIVOUT7_CLK 87 97 #define CLK_AM62LX_POSTDIV4_MAIN_0_HSDIVOUT8_CLK 88 98 #define CLK_AM62LX_POSTDIV4_MAIN_0_HSDIVOUT9_CLK 89 99 #define CLK_AM62LX_POSTDIV4_WKUP_0_HSDIVOUT6_CLK 90 100 #define CLK_AM62LX_POSTDIV4_WKUP_0_HSDIVOUT7_CLK 91 101 #define CLK_AM62LX_POSTDIV4_WKUP_0_HSDIVOUT8_CLK 92 102 #define CLK_AM62LX_POSTDIV4_WKUP_0_HSDIVOUT9_CLK 93 103 #define CLK_AM62LX_RTCSS_WKUP_0_OSC_32K_CLK 94 104 #define CLK_AM62LX_A53_DIVH_CLK4_OBSCLK_OUT_CLK 95 105 #define CLK_AM62LX_SAM62L_A53_256KB_WRAP_MAIN_0_CLKDIV_0_DIVH_CLK4_CLK_CLK 96 106 #define CLK_AM62LX_SAM62L_A53_256KB_WRAP_MAIN_0_CLKDIV_0_DIVP_CLK1_CLK_CLK 97 107 #define CLK_AM62LX_SPI_MAIN_0_IO_CLKSPIO_CLK 98 108 #define CLK_AM62LX_SPI_MAIN_1_IO_CLKSPIO_CLK 99 109 #define CLK_AM62LX_SPI_MAIN_2_IO_CLKSPIO_CLK 100 110 #define CLK_AM62LX_SPI_MAIN_3_IO_CLKSPIO_CLK 101 111 #define CLK_AM62LX_WIZ16B8M4CDT3_MAIN_0_IP1_PPI_M_RXCLKESC_CLK 102 112 #define CLK_AM62LX_WIZ16B8M4CDT3_MAIN_0_IP1_PPI_TXBYTECLKHS_CL_CLK 103 113 #define CLK_AM62LX_CLKOUT0_CTRL_OUT0 104 114 #define CLK_AM62LX_CLK_32K_RC_SEL_OUT0 105 115 #define CLK_AM62LX_MAIN_DPHYTX_REFCLK_OUT0 106 116 #define CLK_AM62LX_MAIN_EMMCSD0_IO_CLKLB_SEL_OUT0 107 117 #define CLK_AM62LX_MAIN_EMMCSD0_REFCLK_SEL_OUT0 108 118 #define CLK_AM62LX_MAIN_EMMCSD1_IO_CLKLB_SEL_OUT0 109 119 #define CLK_AM62LX_MAIN_EMMCSD1_REFCLK_SEL_OUT0 110 120 #define CLK_AM62LX_MAIN_EMMCSD2_IO_CLKLB_SEL_OUT0 111 121 #define CLK_AM62LX_MAIN_EMMCSD2_REFCLK_SEL_OUT0 112 122 #define CLK_AM62LX_MAIN_OSPI_LOOPBACK_CLK_SEL_OUT0 113 123 #define CLK_AM62LX_MAIN_USB0_REFCLK_SEL_OUT0 114 124 #define CLK_AM62LX_MAIN_USB1_REFCLK_SEL_OUT0 115 125 #define CLK_AM62LX_MAIN_WWDTCLKN_SEL_OUT0 116 126 #define CLK_AM62LX_MAIN_WWDTCLKN_SEL_OUT1 117 127 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKR_OUT0 118 128 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKR_OUT1 119 129 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKR_OUT2 120 130 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKX_OUT0 121 131 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKX_OUT1 122 132 #define CLK_AM62LX_MCASPN_AHCLKSEL_AHCLKX_OUT2 123 133 #define CLK_AM62LX_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 124 134 #define CLK_AM62LX_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK 125 135 #define CLK_AM62LX_HSDIV0_16FFT_WKUP_0_HSDIVOUT0_CLK 126 136 #define CLK_AM62LX_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 127 137 #define CLK_AM62LX_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 128 138 #define CLK_AM62LX_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK 129 139 #define CLK_AM62LX_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 130 140 #define CLK_AM62LX_HSDIV4_16FFT_WKUP_0_HSDIVOUT0_CLK 131 141 #define CLK_AM62LX_HSDIV4_16FFT_WKUP_0_HSDIVOUT1_CLK 132 142 #define CLK_AM62LX_HSDIV4_16FFT_WKUP_0_HSDIVOUT2_CLK 133 143 #define CLK_AM62LX_HSDIV4_16FFT_WKUP_0_HSDIVOUT3_CLK 134 144 #define CLK_AM62LX_HSDIV4_16FFT_WKUP_0_HSDIVOUT4_CLK 135 145 #define CLK_AM62LX_SAM62_PLL_CTRL_WRAP_WKUP_0_SYSCLKOUT_CLK 136 146 #define CLK_AM62LX_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK 137 147 #define CLK_AM62LX_ADC0_CLKSEL_OUT0 138 148 #define CLK_AM62LX_AUDIO_REFCLKN_OUT0 139 149 #define CLK_AM62LX_AUDIO_REFCLKN_OUT1 140 150 #define CLK_AM62LX_MAIN_CP_GEMAC_CPTS_CLK_SEL_OUT0 141 151 #define CLK_AM62LX_MAIN_DSS_DPI0_OUT0 142 152 #define CLK_AM62LX_MAIN_GPMC_FCLK_SEL_OUT0 143 153 #define CLK_AM62LX_MAIN_MCANN_CLK_SEL_OUT0 144 154 #define CLK_AM62LX_MAIN_MCANN_CLK_SEL_OUT1 145 155 #define CLK_AM62LX_MAIN_MCANN_CLK_SEL_OUT2 146 156 #define CLK_AM62LX_MAIN_OBSCLK0_MUX_SEL_OUT0 147 157 #define CLK_AM62LX_MAIN_OBSCLK_DIV_OUT0 148 158 #define CLK_AM62LX_MAIN_OBSCLK_OUTMUX_SEL_OUT0 149 159 #define CLK_AM62LX_MAIN_OSPI_REF_CLK_SEL_OUT0 150 160 #define CLK_AM62LX_MAIN_TIMERCLKN_SEL_OUT0 151 161 #define CLK_AM62LX_MAIN_TIMERCLKN_SEL_OUT1 152 162 #define CLK_AM62LX_MAIN_TIMERCLKN_SEL_OUT2 153 163 #define CLK_AM62LX_MAIN_TIMERCLKN_SEL_OUT3 154 164 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT0 155 165 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT1 156 166 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT2 157 167 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT3 158 168 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT4 159 169 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT5 160 170 #define CLK_AM62LX_MAIN_USART_CLKDIV_OUT6 161 171 #define CLK_AM62LX_MCASPN_CLKSEL_AUXCLK_OUT0 162 172 #define CLK_AM62LX_MCASPN_CLKSEL_AUXCLK_OUT1 163 173 #define CLK_AM62LX_MCASPN_CLKSEL_AUXCLK_OUT2 164 174 #define CLK_AM62LX_WKUP_CLKOUT_SEL_OUT0 165 175 #define CLK_AM62LX_WKUP_CLKOUT_SEL_IO_OUT0 166 176 #define CLK_AM62LX_WKUP_GPIO0_CLKSEL_OUT0 167 177 #define CLK_AM62LX_WKUP_GTCCLK_SEL_OUT0 168 178 #define CLK_AM62LX_WKUP_GTC_OUTMUX_SEL_OUT0 169 179 #define CLK_AM62LX_WKUP_OBSCLK_MUX_SEL_OUT0 170 180 #define CLK_AM62LX_WKUP_OBSCLK_OUTMUX_SEL_OUT0 171 181 #define CLK_AM62LX_WKUP_TIMERCLKN_SEL_OUT0 172 182 #define CLK_AM62LX_WKUP_TIMERCLKN_SEL_OUT1 173 183 #define CLK_AM62LX_MAIN_TIMER1_CASCADE_OUT0 174 184 #define CLK_AM62LX_MAIN_TIMER3_CASCADE_OUT0 175 185 #define CLK_AM62LX_WKUP_TIMER1_CASCADE_OUT0 176 186 #define CLK_AM62LX_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV24_CLK_CLK 177 187 188 #endif /* TI_CLK_IDS_H */ 189