Home
last modified time | relevance | path

Searched refs:ulMACBankOffset (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DhalHDCP.c290 MS_U32 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv() local
297 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv()
301 ulMACBankOffset = 0x300; in MHal_HDCP_HDCP14FillBksv()
305 ulMACBankOffset = 0x600; in MHal_HDCP_HDCP14FillBksv()
309 ulMACBankOffset = 0x900; in MHal_HDCP_HDCP14FillBksv()
317 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BIT(10), BIT(10)); in MHal_HDCP_HDCP14FillBksv()
318 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(15)|BIT(14), BIT(15)); // … in MHal_HDCP_HDCP14FillBksv()
320 … MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BMASK(9:0), 0x00); // address in MHal_HDCP_HDCP14FillBksv()
321 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(5), BIT(5)); in MHal_HDCP_HDCP14FillBksv()
325 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x18, BMASK(7:0), pu8BksvData[uctemp… in MHal_HDCP_HDCP14FillBksv()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DhalHDCP.c290 MS_U32 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv() local
297 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv()
301 ulMACBankOffset = 0x300; in MHal_HDCP_HDCP14FillBksv()
305 ulMACBankOffset = 0x600; in MHal_HDCP_HDCP14FillBksv()
309 ulMACBankOffset = 0x900; in MHal_HDCP_HDCP14FillBksv()
317 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BIT(10), BIT(10)); in MHal_HDCP_HDCP14FillBksv()
318 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(15)|BIT(14), BIT(15)); // … in MHal_HDCP_HDCP14FillBksv()
320 … MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BMASK(9:0), 0x00); // address in MHal_HDCP_HDCP14FillBksv()
321 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(5), BIT(5)); in MHal_HDCP_HDCP14FillBksv()
325 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x18, BMASK(7:0), pu8BksvData[uctemp… in MHal_HDCP_HDCP14FillBksv()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DhalHDCP.c290 MS_U32 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv() local
297 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv()
301 ulMACBankOffset = 0x300; in MHal_HDCP_HDCP14FillBksv()
305 ulMACBankOffset = 0x600; in MHal_HDCP_HDCP14FillBksv()
309 ulMACBankOffset = 0x900; in MHal_HDCP_HDCP14FillBksv()
317 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BIT(10), BIT(10)); in MHal_HDCP_HDCP14FillBksv()
318 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(15)|BIT(14), BIT(15)); // … in MHal_HDCP_HDCP14FillBksv()
320 … MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BMASK(9:0), 0x00); // address in MHal_HDCP_HDCP14FillBksv()
321 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(5), BIT(5)); in MHal_HDCP_HDCP14FillBksv()
325 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x18, BMASK(7:0), pu8BksvData[uctemp… in MHal_HDCP_HDCP14FillBksv()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c443 MS_U32 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv() local
450 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv()
454 ulMACBankOffset = 0x300; in MHal_HDCP_HDCP14FillBksv()
458 ulMACBankOffset = 0x600; in MHal_HDCP_HDCP14FillBksv()
462 ulMACBankOffset = 0x900; in MHal_HDCP_HDCP14FillBksv()
470 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BIT(10), BIT(10)); in MHal_HDCP_HDCP14FillBksv()
471 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(15)|BIT(14), BIT(15)); // … in MHal_HDCP_HDCP14FillBksv()
473 … MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BMASK(9:0), 0x00); // address in MHal_HDCP_HDCP14FillBksv()
474 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(5), BIT(5)); in MHal_HDCP_HDCP14FillBksv()
478 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x18, BMASK(7:0), pu8BksvData[uctemp… in MHal_HDCP_HDCP14FillBksv()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c449 MS_U32 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv() local
456 ulMACBankOffset = 0; in MHal_HDCP_HDCP14FillBksv()
460 ulMACBankOffset = 0x300; in MHal_HDCP_HDCP14FillBksv()
464 ulMACBankOffset = 0x600; in MHal_HDCP_HDCP14FillBksv()
468 ulMACBankOffset = 0x900; in MHal_HDCP_HDCP14FillBksv()
476 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BIT(10), BIT(10)); in MHal_HDCP_HDCP14FillBksv()
477 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(15)|BIT(14), BIT(15)); // … in MHal_HDCP_HDCP14FillBksv()
479 … MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x17, BMASK(9:0), 0x00); // address in MHal_HDCP_HDCP14FillBksv()
480 MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x19, BIT(5), BIT(5)); in MHal_HDCP_HDCP14FillBksv()
484 …MHalHdcpRegMaskWrite(DEF_HDCP14_RX_REG_BANK +ulMACBankOffset, 0x18, BMASK(7:0), pu8BksvData[uctemp… in MHal_HDCP_HDCP14FillBksv()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3365 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_PowerSavingSetting() local
3371 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_PowerSavingSetting()
3376 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_PowerSavingSetting()
3381 ulMACBankOffset = 0x0600; // BK 0x171600 in _Hal_tmds_PowerSavingSetting()
3386 ulMACBankOffset = 0x0900; // BK 0x171900 in _Hal_tmds_PowerSavingSetting()
3401 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_02_L +ulMACBankOffset, 0x640, BMASK(15:4)); in _Hal_tmds_PowerSavingSetting()
3406 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_00_L +ulMACBankOffset, 0, BIT(0)); in _Hal_tmds_PowerSavingSetting()
3424 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_GetPowerSavingDoneFlag() local
3429 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_GetPowerSavingDoneFlag()
3433 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_GetPowerSavingDoneFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3368 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_PowerSavingSetting() local
3374 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_PowerSavingSetting()
3379 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_PowerSavingSetting()
3384 ulMACBankOffset = 0x0600; // BK 0x171600 in _Hal_tmds_PowerSavingSetting()
3389 ulMACBankOffset = 0x0900; // BK 0x171900 in _Hal_tmds_PowerSavingSetting()
3404 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_02_L +ulMACBankOffset, 0x640, BMASK(15:4)); in _Hal_tmds_PowerSavingSetting()
3409 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_00_L +ulMACBankOffset, 0, BIT(0)); in _Hal_tmds_PowerSavingSetting()
3427 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_GetPowerSavingDoneFlag() local
3432 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_GetPowerSavingDoneFlag()
3436 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_GetPowerSavingDoneFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3368 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_PowerSavingSetting() local
3374 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_PowerSavingSetting()
3379 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_PowerSavingSetting()
3384 ulMACBankOffset = 0x0600; // BK 0x171600 in _Hal_tmds_PowerSavingSetting()
3389 ulMACBankOffset = 0x0900; // BK 0x171900 in _Hal_tmds_PowerSavingSetting()
3404 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_02_L +ulMACBankOffset, 0x640, BMASK(15:4)); in _Hal_tmds_PowerSavingSetting()
3409 W2BYTEMSK(REG_DVI_RSV_DUAL_P0_00_L +ulMACBankOffset, 0, BIT(0)); in _Hal_tmds_PowerSavingSetting()
3427 MS_U32 ulMACBankOffset = 0; in _Hal_tmds_GetPowerSavingDoneFlag() local
3432 ulMACBankOffset = 0x0000; // BK 0x171000 in _Hal_tmds_GetPowerSavingDoneFlag()
3436 ulMACBankOffset = 0x0300; // BK 0x171300 in _Hal_tmds_GetPowerSavingDoneFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c6193 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6198 ulMACBankOffset = 0x0000; // BK 0x171000 in Hal_HDCP_WriteDoneInterruptEnable()
6205 ulMACBankOffset = 0x0300; // BK 0x171300 in Hal_HDCP_WriteDoneInterruptEnable()
6212 ulMACBankOffset = 0x0600; // BK 0x171600 in Hal_HDCP_WriteDoneInterruptEnable()
6219 ulMACBankOffset = 0x0900; // BK 0x171900 in Hal_HDCP_WriteDoneInterruptEnable()
6230 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6231 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6232 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c6314 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6319 ulMACBankOffset = 0x0000; // BK 0x171000 in Hal_HDCP_WriteDoneInterruptEnable()
6326 ulMACBankOffset = 0x0300; // BK 0x171300 in Hal_HDCP_WriteDoneInterruptEnable()
6333 ulMACBankOffset = 0x0600; // BK 0x171600 in Hal_HDCP_WriteDoneInterruptEnable()
6340 ulMACBankOffset = 0x0900; // BK 0x171900 in Hal_HDCP_WriteDoneInterruptEnable()
6351 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6352 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6353 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c6684 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6689 ulMACBankOffset = 0x0000; // BK 0x171000 in Hal_HDCP_WriteDoneInterruptEnable()
6696 ulMACBankOffset = 0x0300; // BK 0x171300 in Hal_HDCP_WriteDoneInterruptEnable()
6703 ulMACBankOffset = 0x0600; // BK 0x171600 in Hal_HDCP_WriteDoneInterruptEnable()
6710 ulMACBankOffset = 0x0900; // BK 0x171900 in Hal_HDCP_WriteDoneInterruptEnable()
6721 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6722 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6723 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c6684 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6689 ulMACBankOffset = 0x0000; // BK 0x171000 in Hal_HDCP_WriteDoneInterruptEnable()
6696 ulMACBankOffset = 0x0300; // BK 0x171300 in Hal_HDCP_WriteDoneInterruptEnable()
6703 ulMACBankOffset = 0x0600; // BK 0x171600 in Hal_HDCP_WriteDoneInterruptEnable()
6710 ulMACBankOffset = 0x0900; // BK 0x171900 in Hal_HDCP_WriteDoneInterruptEnable()
6721 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6722 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6723 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c6238 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6240 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6241 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6242 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c6316 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6318 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6319 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6320 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c6238 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6240 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6241 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6242 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c6316 MS_U32 ulMACBankOffset = 0; in Hal_HDCP_WriteDoneInterruptEnable() local
6318 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_3B_L +ulMACBankOffset, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
6319 W2BYTEMSK(REG_HDCP_DUAL_P0_15_L +ulMACBankOffset, bEnableIRQ? 0: BIT(15), BIT(15)); in Hal_HDCP_WriteDoneInterruptEnable()
6320 … W2BYTEMSK(REG_HDCP_DUAL_P0_67_L +ulMACBankOffset, bEnableIRQ? 0: BIT(3)| BIT(2), BIT(3)| BIT(2)); in Hal_HDCP_WriteDoneInterruptEnable()