Searched refs:_RegCtrl1 (Results 1 – 1 of 1) sorted by relevance
39 static REG_Ctrl1* _RegCtrl1[4] = {NULL}; // PVR_IframeLUT FSC variable129 _RegCtrl1[0] = (REG_Ctrl1*)(u32BankAddr + 0xE6E00UL); // PVR_IframeLUT FSC 0x1737 in _HAL_PVR_IframeLUT_SetBank()130 _RegCtrl1[1] = (REG_Ctrl1*)(u32BankAddr + 0xE6E80UL); // PVR_IframeLUT FSC 0x1737 in _HAL_PVR_IframeLUT_SetBank()131 _RegCtrl1[2] = (REG_Ctrl1*)(u32BankAddr + 0xE6F00UL); // PVR_IframeLUT FSC 0x1737 in _HAL_PVR_IframeLUT_SetBank()132 _RegCtrl1[3] = (REG_Ctrl1*)(u32BankAddr + 0xE6F80UL); // PVR_IframeLUT FSC 0x1737 in _HAL_PVR_IframeLUT_SetBank()267 _REG16_SET_PVR_IframeLUT(&_RegCtrl1[u32PVREng]->CFG1_01, 0x0FE0); in HAL_PVR_IframeLUT_Open()295 _REG16_SET_PVR_IframeLUT(&_RegCtrl1[u32PVREng]->CFG1_01, 0x0FE0); in HAL_PVR_IframeLUT_Close()307 … _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_MPGE); in HAL_PVR_IframeLUT_SetVdecType()310 … _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_H264); in HAL_PVR_IframeLUT_SetVdecType()313 … _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_HEVC); in HAL_PVR_IframeLUT_SetVdecType()[all …]