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Searched refs:_RV1 (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
104 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
105 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end
106 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
107 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
108 _RV1(L_BK_VE_ENC(0x03), 0x07),
109 _RV1(H_BK_VE_ENC(0x03), 0x00),
110 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
111 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast
112 _RV1(L_BK_VE_ENC(0x05), 0x77),// burst phase offset
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
104 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
105 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end
106 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
107 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
108 _RV1(L_BK_VE_ENC(0x03), 0x07),
109 _RV1(H_BK_VE_ENC(0x03), 0x00),
110 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
111 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast
112 _RV1(L_BK_VE_ENC(0x05), 0x77),// burst phase offset
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
104 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
105 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end
106 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
107 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
108 _RV1(L_BK_VE_ENC(0x03), 0x07),
109 _RV1(H_BK_VE_ENC(0x03), 0x00),
110 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
111 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast
112 _RV1(L_BK_VE_ENC(0x05), 0x77),// burst phase offset
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
104 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
105 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end
106 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
107 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
108 _RV1(L_BK_VE_ENC(0x03), 0x07),
109 _RV1(H_BK_VE_ENC(0x03), 0x00),
110 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
111 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast
112 _RV1(L_BK_VE_ENC(0x05), 0x77),// burst phase offset
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/M7621/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/mainz/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/maserati/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/maxim/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/messi/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/manhattan/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/M7821/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/macan/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/mustang/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/maldives/ve/include/
H A Dmhal_tvencoder_tbl.h98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)… macro
105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start
106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end
107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start
108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end
109 _RV1(L_BK_VE_ENC(0x02), 0x00),
110 _RV1(H_BK_VE_ENC(0x02), 0x00),
111 _RV1(L_BK_VE_ENC(0x03), 0x00),
112 _RV1(H_BK_VE_ENC(0x03), 0x00),
113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c122 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
2712 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
2713 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
2715 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
2716 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
2717 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
2718 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
2719 _RV1(BK_AFEC_2F, 0x84),
2720 _RV1(BK_AFEC_38, 0x13),
2721 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c121 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6056 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6057 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6059 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6060 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6061 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6062 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6063 _RV1(BK_AFEC_2F, 0x84),
6064 _RV1(BK_AFEC_38, 0x13),
6065 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c127 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6064 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6065 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6068 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6069 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6070 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6071 _RV1(BK_AFEC_2F, 0x84),
6072 _RV1(BK_AFEC_38, 0x13),
6073 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c127 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6064 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6065 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6068 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6069 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6070 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6071 _RV1(BK_AFEC_2F, 0x84),
6072 _RV1(BK_AFEC_38, 0x13),
6073 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c126 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6063 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6064 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6066 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6067 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6068 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6069 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6070 _RV1(BK_AFEC_2F, 0x84),
6071 _RV1(BK_AFEC_38, 0x13),
6072 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c127 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6064 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6065 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6068 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6069 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6070 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6071 _RV1(BK_AFEC_2F, 0x84),
6072 _RV1(BK_AFEC_38, 0x13),
6073 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c121 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6056 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6057 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6059 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6060 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6061 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6062 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6063 _RV1(BK_AFEC_2F, 0x84),
6064 _RV1(BK_AFEC_38, 0x13),
6065 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c122 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
2712 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
2713 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
2715 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
2716 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
2717 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
2718 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
2719 _RV1(BK_AFEC_2F, 0x84),
2720 _RV1(BK_AFEC_38, 0x13),
2721 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c127 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6064 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6065 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6068 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6069 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6070 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6071 _RV1(BK_AFEC_2F, 0x84),
6072 _RV1(BK_AFEC_38, 0x13),
6073 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c127 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
6064 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
6065 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6068 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
6069 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
6070 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
6071 _RV1(BK_AFEC_2F, 0x84),
6072 _RV1(BK_AFEC_38, 0x13),
6073 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c121 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (MS_U8)(addr), (MS_U8)(value) macro
2711 _RV1(BK_AFEC_E3, 0x20), // fixed color stripe issue
2712 _RV1(BK_AFEC_69, 0x80), // 3569[6]=0 ,HK mcu is fast VD
2714 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
2715 _RV1(BK_AFEC_18, 0x16), // Brian 20110318 HW add new function to fix the chess board issue
2716 _RV1(BK_AFEC_1E, 0xC8), // BY 20090628 enable ADC 4x
2717 _RV1(BK_AFEC_21, 0x19), // REG_3521[0]=1 Disable Digial Clamp S/W Reset
2718 _RV1(BK_AFEC_2F, 0x84),
2719 _RV1(BK_AFEC_38, 0x13),
2720 _RV1(BK_AFEC_B4, 0x7C), // fixed color stripe issue
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