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Searched refs:_PK_L_ (Results 1 – 25 of 121) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_sc.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A Dcolor_reg.h154 #define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) macro
162 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
164 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
166 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
168 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
170 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
172 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
174 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
176 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
178 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/maldives/dlc/include/
H A Dhwreg_dlc.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
111 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
113 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
115 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
117 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
119 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
121 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
123 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
125 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
127 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/mustang/dlc/include/
H A Dhwreg_dlc.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
111 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
113 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
115 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
117 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
119 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
121 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
123 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
125 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
127 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h100 #define _PK_L_(bank, addr) (((MS_U16)(bank) << 8) | (MS_U16)((addr)*2)) macro
109 #define REG_SC_BK00_00_L _PK_L_(0x00, 0x00)
111 #define REG_SC_BK00_01_L _PK_L_(0x00, 0x01)
113 #define REG_SC_BK00_02_L _PK_L_(0x00, 0x02)
115 #define REG_SC_BK00_03_L _PK_L_(0x00, 0x03)
117 #define REG_SC_BK00_04_L _PK_L_(0x00, 0x04)
119 #define REG_SC_BK00_05_L _PK_L_(0x00, 0x05)
121 #define REG_SC_BK00_06_L _PK_L_(0x00, 0x06)
123 #define REG_SC_BK00_07_L _PK_L_(0x00, 0x07)
125 #define REG_SC_BK00_08_L _PK_L_(0x00, 0x08)
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