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Searched refs:W2BYTE (Results 1 – 25 of 138) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A DhalDAC.c567 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 12:12); in _HAL_DAC_HpdIsr()
568 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 14:14); in _HAL_DAC_HpdIsr()
569 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0x2422, 15:0); in _HAL_DAC_HpdIsr()
570 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0); in _HAL_DAC_HpdIsr()
571 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 15:12); in _HAL_DAC_HpdIsr()
572 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11); in _HAL_DAC_HpdIsr()
575 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 4:4); in _HAL_DAC_HpdIsr()
576 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 4:4); in _HAL_DAC_HpdIsr()
584 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12); in _HAL_DAC_HpdIsr()
585 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14); in _HAL_DAC_HpdIsr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
H A Dmhal_hdmi.c1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2006 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2016 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3614 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3643 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3665 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3714 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3760 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3800 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
H A Dmhal_hdmi.c1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2006 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2016 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3614 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3643 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3665 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3714 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3760 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3800 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
H A Dmhal_hdmi.c1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2006 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2016 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3611 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3640 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3662 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3711 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3757 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
3797 W2BYTE(REG_HDCP_DUAL_P0_01_L +ulMACBankOffset, 0xFFFF); in _Hal_tmds_PowerSavingStateProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c227 … W2BYTE(REG_DVI_DTOP_DUAL_P0_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
249 … W2BYTE(REG_DVI_DTOP_DUAL_P1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
272 … W2BYTE(REG_DVI_DTOP_DUAL_P2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
295 … W2BYTE(REG_DVI_DTOP_DUAL_P3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
325 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_SC_mux_set_dvi_mux()
326 W2BYTE(REG_COMBO_PHY0_P1_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
327 W2BYTE(REG_COMBO_PHY0_P1_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
328 W2BYTE(REG_COMBO_PHY0_P2_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
329 W2BYTE(REG_COMBO_PHY0_P2_0C_L, 0x1008); in Hal_SC_mux_set_dvi_mux()
[all …]
H A Dmhal_hdmi.c2051 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2061 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2071 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2081 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3325 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3326 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3346 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3347 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3348 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3370 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A DhalDAC.c987 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 12:12); in _HAL_DAC_HpdIsr()
988 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 14:14); in _HAL_DAC_HpdIsr()
989 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0x2422, 15:0); in _HAL_DAC_HpdIsr()
990 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0); in _HAL_DAC_HpdIsr()
991 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 15:12); in _HAL_DAC_HpdIsr()
992 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11); in _HAL_DAC_HpdIsr()
995 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 4:4); in _HAL_DAC_HpdIsr()
996 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 4:4); in _HAL_DAC_HpdIsr()
1004 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12); in _HAL_DAC_HpdIsr()
1005 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14); in _HAL_DAC_HpdIsr()
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A DhalDAC.c987 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 12:12); in _HAL_DAC_HpdIsr()
988 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 14:14); in _HAL_DAC_HpdIsr()
989 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0x2422, 15:0); in _HAL_DAC_HpdIsr()
990 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0); in _HAL_DAC_HpdIsr()
991 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 15:12); in _HAL_DAC_HpdIsr()
992 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11); in _HAL_DAC_HpdIsr()
995 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 4:4); in _HAL_DAC_HpdIsr()
996 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 4:4); in _HAL_DAC_HpdIsr()
1004 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12); in _HAL_DAC_HpdIsr()
1005 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14); in _HAL_DAC_HpdIsr()
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A DhalDAC.c987 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 12:12); in _HAL_DAC_HpdIsr()
988 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 14:14); in _HAL_DAC_HpdIsr()
989 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0x2422, 15:0); in _HAL_DAC_HpdIsr()
990 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0); in _HAL_DAC_HpdIsr()
991 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 15:12); in _HAL_DAC_HpdIsr()
992 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11); in _HAL_DAC_HpdIsr()
995 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 4:4); in _HAL_DAC_HpdIsr()
996 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 4:4); in _HAL_DAC_HpdIsr()
1004 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12); in _HAL_DAC_HpdIsr()
1005 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14); in _HAL_DAC_HpdIsr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c296 W2BYTE(REG_HDCP22_P0_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
297 W2BYTE(REG_DVI_ATOP_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
298 W2BYTE(REG_DVI_ATOP_71_L, 0); in Hal_HDCP22_PollingWriteDone()
308 W2BYTE(REG_HDCP22_P1_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
309 W2BYTE(REG_DVI_ATOP1_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
310 W2BYTE(REG_DVI_ATOP1_71_L, 0); in Hal_HDCP22_PollingWriteDone()
320 W2BYTE(REG_HDCP22_P2_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
321 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
322 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingWriteDone()
332 W2BYTE(REG_HDCP22_P3_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
[all …]
H A Dmhal_mux.c234 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
269 … W2BYTE( REG_DVI_DTOP1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
305 … W2BYTE( REG_DVI_DTOP2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
340 … W2BYTE( REG_DVI_DTOP3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
387 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_DVI_ATOP_60_L, 0); // enable DVI0 PLL power in Hal_SC_mux_set_dvi_mux()
393 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
394 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
395 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
408 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c296 W2BYTE(REG_HDCP22_P0_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
297 W2BYTE(REG_DVI_ATOP_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
298 W2BYTE(REG_DVI_ATOP_71_L, 0); in Hal_HDCP22_PollingWriteDone()
308 W2BYTE(REG_HDCP22_P1_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
309 W2BYTE(REG_DVI_ATOP1_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
310 W2BYTE(REG_DVI_ATOP1_71_L, 0); in Hal_HDCP22_PollingWriteDone()
320 W2BYTE(REG_HDCP22_P2_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
321 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
322 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingWriteDone()
332 W2BYTE(REG_HDCP22_P3_34_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
[all …]
H A Dmhal_mux.c234 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
269 … W2BYTE( REG_DVI_DTOP1_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
305 … W2BYTE( REG_DVI_DTOP2_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
340 … W2BYTE( REG_DVI_DTOP3_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
387 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_DVI_ATOP_60_L, 0); // enable DVI0 PLL power in Hal_SC_mux_set_dvi_mux()
393 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
394 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
395 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
408 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1364 W2BYTE(REG_HDMI_DUAL_0_02_L, usPacketStatus); in _Hal_tmds_GetPacketReceiveFlag()
1412 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
1413 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
1414 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, 0); in Hal_HDCP22_PollingWriteDone()
1889 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_HDMI_init()
1890 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_HDMI_init()
1893 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_HDMI_init()
1902 W2BYTE(REG_HDMI_DUAL_0_07_L, 0x0001); // PIP0 enable deep color in Hal_HDMI_init()
1906 W2BYTE(REG_COMBO_PHY0_P0_5A_L, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
1907 W2BYTE(REG_COMBO_PHY0_P0_0A_L, 0x0040);// [6]: reg_af_ls_20out_sel=1 in Hal_HDMI_init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c1008 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
1930 W2BYTE(REG_HDMI_DUAL_0_02_L, usPacketStatus); in _Hal_tmds_GetPacketReceiveFlag()
2115 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
2116 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
2117 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, 0); in Hal_HDCP22_PollingWriteDone()
2356 W2BYTE(REG_HDCP_DUAL_P0_1B_L, BIT(9)); in Hal_HDCP_GetEncryptionFlag()
2624 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_HDMI_init()
2625 W2BYTE(REG_COMBO_PHY0_P0_0C_L, 0x3FFF); in Hal_HDMI_init()
2628 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_HDMI_init()
2637 W2BYTE(REG_HDMI_DUAL_0_07_L, 0x0001); // PIP0 enable deep color in Hal_HDMI_init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c2005 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2015 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2025 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2035 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3430 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3431 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3451 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3452 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3453 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3475 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c2005 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2015 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2025 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2035 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3430 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3431 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3451 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3452 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3453 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3475 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c2044 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2054 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2064 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2074 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3341 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3342 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3366 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3367 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3368 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3394 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c2044 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2054 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2064 W2BYTE(REG_HDCP_DUAL_P2_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2074 W2BYTE(REG_HDCP_DUAL_P3_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3341 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3342 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3366 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3367 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3368 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3394 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
[all …]

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