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Searched refs:VOP_SEL_CLK_432 (Results 1 – 5 of 5) sorted by relevance

/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h480 #define VOP_SEL_CLK_432 (BIT0 | BIT1 | BIT2 | BIT3) macro
H A DhalMVOP.c3219 HAL_WriteByteMask(REG_CKG_FBDEC, 0x0, VOP_SEL_CLK_432); //default disable mfdec clock. in HAL_MVOP_ResetReg()
3305 … HAL_WriteByteMask(SUB_REG(REG_CKG_FBDEC), 0x0, VOP_SEL_CLK_432); //default disable mfdec clock. in HAL_MVOP_ResetReg()
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h490 #define VOP_SEL_CLK_432 (BIT0 | BIT1 | BIT2 | BIT3) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h546 #define VOP_SEL_CLK_432 (BIT0 | BIT1 | BIT2 | BIT3) macro
H A DhalMVOP.c3284 HAL_WriteByteMask(REG_CKG_FBDEC, 0x0, VOP_SEL_CLK_432); //default disable mfdec clock. in HAL_MVOP_ResetReg()
3374 … HAL_WriteByteMask(SUB_REG(REG_CKG_FBDEC), 0x0, VOP_SEL_CLK_432); //default disable mfdec clock. in HAL_MVOP_ResetReg()