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Searched refs:VD_MHEG5_REG_BASE (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/messi/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/mvd/
H A DregMVD.h112 #define VD_MHEG5_REG_BASE 0x0300 macro
151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4)
152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2)
154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0)
157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0)