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Searched refs:VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR1_END (Results 1 – 3 of 3) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h540 …#define VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR1_END BITS(11:8, 4) // configure 2nd secur… macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h540 …#define VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR1_END BITS(11:8, 4) // configure 2nd secur… macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h540 …#define VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR1_END BITS(11:8, 4) // configure 2nd secur… macro