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Searched refs:UART_LSR_THRE (Results 1 – 25 of 48) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1033 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1142 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1255 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1386 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h268 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
397 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1033 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1142 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1225 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1356 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h268 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
397 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1033 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1142 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1225 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1356 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h268 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
397 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1033 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1142 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1274 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1405 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DhalUART.c587 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
604 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
721 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
820 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
886 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1037 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1054 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1161 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1244 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1421 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h267 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
396 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1035 while ((!(UART_REG8(UART_LSR) & UART_LSR_THRE)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Write()
1052 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1161 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1256 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1409 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h274 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
403 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1035 while ((!(UART_REG8(UART_LSR) & UART_LSR_THRE)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Write()
1052 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1161 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1256 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1409 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h269 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
398 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c612 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
629 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
746 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
845 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
911 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1062 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1079 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1186 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1274 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1444 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h289 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
418 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c611 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
628 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
745 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
844 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
910 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1061 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1078 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1185 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1272 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1449 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h267 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
396 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1082 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1189 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1328 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1523 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1082 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1189 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1328 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1523 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h305 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
434 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1082 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1189 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1328 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1523 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c614 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
631 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
748 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
847 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
913 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1064 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1081 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1188 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1326 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1496 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1082 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1189 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1331 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1526 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h309 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty macro
438 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c657 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
674 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
791 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
890 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
956 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1107 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
1124 if (!(UART_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_PIU_Write()
1231 if (UART_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_PIU_Poll()
1318 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr()
1495 while ((UART_REG8(UART_LSR) & UART_LSR_THRE) in _HAL_UART_PIU_Isr_HalReg()

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