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Searched refs:UART_LSR_DR (Results 1 – 25 of 48) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DhalUART.c639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1086 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1125 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1223 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1354 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h263 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DhalUART.c639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1086 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1125 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1193 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1324 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h263 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DhalUART.c639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1086 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1125 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1193 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1324 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h263 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DhalUART.c639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1086 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1125 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1242 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1373 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DhalUART.c660 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
704 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
788 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
854 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1105 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1144 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1212 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1389 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h262 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
784 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
850 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1105 while ((!(UART_REG8(UART_LSR) & UART_LSR_DR)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Read()
1144 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1224 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1377 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h269 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
784 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
850 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1105 while ((!(UART_REG8(UART_LSR) & UART_LSR_DR)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Read()
1144 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1224 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1377 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h264 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c685 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
729 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
813 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
879 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1130 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1169 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1242 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1412 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h284 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c684 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
728 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
812 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
878 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1129 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1168 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1240 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1417 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h262 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1133 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1172 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1296 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1491 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1133 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1172 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1296 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1491 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1133 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1172 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1296 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1491 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c687 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
731 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
815 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
881 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1132 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1171 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1294 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1464 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1133 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1172 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1299 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1494 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
H A DregUART.h304 #define UART_LSR_DR 0x01 // Receiver data ready macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c730 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
774 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
858 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
924 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
1175 while (!(UART_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_PIU_Read()
1214 if (UART_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_PIU_Poll()
1286 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr()
1463 while (UART_REG8(UART_LSR) & UART_LSR_DR) in _HAL_UART_PIU_Isr_HalReg()
/utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/linux/
H A Dserial_reg.h120 #define UART_LSR_DR 0x01 /* Receiver data ready */ macro

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