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Searched refs:UART_LCR (Results 1 – 25 of 60) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/sc/hal/k6/sc/
H A DhalSC.c184 SC_OR(u8SCID,UART_LCR, UART_LCR_DLAB); in _HAL_SC_GetLsr()
186 SC_AND(u8SCID,UART_LCR, ~(UART_LCR_DLAB)); in _HAL_SC_GetLsr()
322 SC_WRITE(u8SCID,UART_LCR, UART_LCR_SBC); //I/O in HAL_SC_Init()
896 …SC_OR(u8SCID,UART_LCR, UART_LCR_DLAB); // Line Control Register in HAL_SC_SetUartDiv()
899 SC_AND(u8SCID,UART_LCR, ~(UART_LCR_DLAB)); // Line Control Register in HAL_SC_SetUartDiv()
909 SC_WRITE(u8SCID,UART_LCR, (SC_READ(u8SCID,UART_LCR)&0xE0) | u8UartMode); in HAL_SC_SetUartMode()
1107 SC_OR(u8SCID, UART_LCR, UART_LCR_SBC); // As general I/O pin, idle is logical high in HAL_SC_InputOutputPadCtrl()
1112 SC_AND(u8SCID, UART_LCR, ~UART_LCR_SBC); // I/O pin forced to logical low in HAL_SC_InputOutputPadCtrl()
/utopia/UTPA2-700.0.x/modules/sc/hal/k6lite/sc/
H A DhalSC.c379 SC_WRITE(u8SCID,UART_LCR, UART_LCR_SBC); //I/O in HAL_SC_Init()
887 …SC_OR(u8SCID,UART_LCR, UART_LCR_DLAB); // Line Control Register in HAL_SC_SetUartDiv()
890 SC_AND(u8SCID,UART_LCR, ~(UART_LCR_DLAB)); // Line Control Register in HAL_SC_SetUartDiv()
900 SC_WRITE(u8SCID,UART_LCR, (SC_READ(u8SCID,UART_LCR)&0xE0) | u8UartMode); in HAL_SC_SetUartMode()
1098 SC_OR(u8SCID, UART_LCR, UART_LCR_SBC); // As general I/O pin, idle is logical high in HAL_SC_InputOutputPadCtrl()
1103 SC_AND(u8SCID, UART_LCR, ~UART_LCR_SBC); // I/O pin forced to logical low in HAL_SC_InputOutputPadCtrl()
/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DhalUART.c743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
746 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
975 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1200 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1203 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1494 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DhalUART.c743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
746 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
975 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1170 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1173 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1464 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h177 #define UART_LCR 3 // Out: Line Control Register macro
191 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DhalUART.c743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
746 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
975 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1170 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1173 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1464 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h177 #define UART_LCR 3 // Out: Line Control Register macro
191 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DhalUART.c743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
746 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
975 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1219 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1222 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1513 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DhalUART.c764 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
767 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
996 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1189 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1192 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1554 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h176 #define UART_LCR 3 // Out: Line Control Register macro
190 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c760 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
763 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
992 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1198 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1203 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1522 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h183 #define UART_LCR 3 // Out: Line Control Register macro
197 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c760 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
763 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
992 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1198 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1203 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1522 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h178 #define UART_LCR 3 // Out: Line Control Register macro
192 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c789 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
792 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1021 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1217 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1220 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1583 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h198 #define UART_LCR 3 // Out: Line Control Register macro
212 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c788 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
791 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1020 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1216 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1219 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1583 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
H A DregUART.h176 #define UART_LCR 3 // Out: Line Control Register macro
190 #define UART_LCR (3 * 2) // Out: Line Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
795 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1024 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1271 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1274 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1680 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
795 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1024 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1271 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1274 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1680 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
795 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1024 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1271 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1274 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1680 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c791 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
794 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1023 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1270 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1273 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1635 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
795 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1024 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1274 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1277 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1683 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c834 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
837 AEON_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_Aeon_Set_Baudrate()
1066 AEON_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_Aeon_Open()
1262 UART_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_PIU_Set_Baudrate()
1265 UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); in HAL_UART_PIU_Set_Baudrate()
1629 UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); in HAL_UART_PIU_Open()
/utopia/UTPA2-700.0.x/modules/sc/drv/sc/sc2/
H A DdrvSC.c773 …SC_OR(u8SCID,UART_LCR, UART_LCR_DLAB); // Line Control Register in _SC_SetUartDiv()
776 SC_AND(u8SCID,UART_LCR, ~(UART_LCR_DLAB)); // Line Control Register in _SC_SetUartDiv()
788 SC_WRITE(u8SCID,UART_LCR, (SC_READ(u8SCID,UART_LCR)&0xE0)|_scInfo[u8SCID].u8UartMode); in _SC_SetUartMode()
1480 SC_AND(u8SCID,UART_LCR, ~UART_LCR_SBC); //I/O in _SC_Activate()
1517 SC_AND(u8SCID,UART_LCR, ~UART_LCR_SBC); //I/O in _SC_Activate()
1552 SC_OR(u8SCID,UART_LCR, UART_LCR_SBC); //I/O in _SC_Deactivate()
2228 SC_WRITE(u8SCID,UART_LCR, UART_LCR_SBC); //I/O low in _SC_Task_Proc()
2286 SC_AND(u8SCID,UART_LCR, ~UART_LCR_SBC); //I/O in _SC_Task_Proc()
2353 SC_OR(u8SCID,UART_LCR, UART_LCR_SBC); //I/O in _SC_Task_Proc()
2414 SC_AND(u8SCID,UART_LCR, ~UART_LCR_SBC); //I/O in _SC_Task_Proc()
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