Searched refs:UADP_SPT_0NXT (Results 1 – 11 of 11) sorted by relevance
40 UADP_SPT_0NXT(WDT_INIT_PARAM); in WDT_adp_Init()41 UADP_SPT_0NXT(WDT_STOP_PARAM); in WDT_adp_Init()42 UADP_SPT_0NXT(WDT_SET_S_PARAM); in WDT_adp_Init()43 UADP_SPT_0NXT(WDT_SET_MS_PARAM); in WDT_adp_Init()44 UADP_SPT_0NXT(WDT_SET_US_PARAM); in WDT_adp_Init()45 UADP_SPT_0NXT(WDT_SETTIMER_PARAM); in WDT_adp_Init()46 UADP_SPT_0NXT(TIMER_COUNT_PARAM); in WDT_adp_Init()47 UADP_SPT_0NXT(TIMER_INT_PARAM); in WDT_adp_Init()48 UADP_SPT_0NXT(TIMER_HIT_MAX_MATCH_PARAM); in WDT_adp_Init()49 UADP_SPT_0NXT(TIMER_RST_PARAM); in WDT_adp_Init()[all …]
63 UADP_SPT_0NXT(VBI_DrvStatus); in VBI_adp_Init()64 UADP_SPT_0NXT(MS_PHYADDR); in VBI_adp_Init()65 UADP_SPT_0NXT(VBI_CC_TABLE); in VBI_adp_Init()68 UADP_SPT_0NXT(VBI_BOOL); in VBI_adp_Init()69 UADP_SPT_0NXT(VBI_GET_DATA); in VBI_adp_Init()70 UADP_SPT_0NXT(VBI_GETINFO_PARAM); in VBI_adp_Init()71 UADP_SPT_0NXT(VBI_SETDBGLEVEL_PARAM); in VBI_adp_Init()72 UADP_SPT_0NXT(VBI_CMD); in VBI_adp_Init()73 UADP_SPT_0NXT(VBI_INIT_TYPE_PARAM); in VBI_adp_Init()74 UADP_SPT_0NXT(DMX_TTX_CMD); in VBI_adp_Init()[all …]
50 UADP_SPT_0NXT(MIU_RET); in MIU_adp_Init()51 UADP_SPT_0NXT(MIU_MIU_MASK); in MIU_adp_Init()52 UADP_SPT_0NXT(MIU_MIUREQ_MASK); in MIU_adp_Init()53 UADP_SPT_0NXT(MIU_SET_SSC); in MIU_adp_Init()54 UADP_SPT_0NXT(MIU_SET_SSCVALUE); in MIU_adp_Init()55 UADP_SPT_0NXT(MIU_PROYECT_ID); in MIU_adp_Init()56 UADP_SPT_0NXT(MIU_SELMIU); in MIU_adp_Init()57 UADP_SPT_0NXT(MIU_PortectInfo); in MIU_adp_Init()58 UADP_SPT_0NXT(MIU_GroupPriority); in MIU_adp_Init()59 UADP_SPT_0NXT(MIU_DRAM_SIZE); in MIU_adp_Init()[all …]
30 UADP_SPT_0NXT(IRTX_SETSTATUS_PARAM); in IR_TX_adp_Init()31 UADP_SPT_0NXT(IRTX_SETMEMSTATUS_PARAM); in IR_TX_adp_Init()32 UADP_SPT_0NXT(IRTX_SETCLKDIV_PARAM); in IR_TX_adp_Init()33 UADP_SPT_0NXT(IRTX_SETDELAYCLKTIME_PARAM); in IR_TX_adp_Init()34 UADP_SPT_0NXT(IRTX_SETMEMADDR_PARAM); in IR_TX_adp_Init()35 UADP_SPT_0NXT(IRTX_SETMEMDATA_PARAM); in IR_TX_adp_Init()36 UADP_SPT_0NXT(IRTX_SETUNITVALUE_PARAM); in IR_TX_adp_Init()37 UADP_SPT_0NXT(IRTX_SETSHOTCOUNT_PARAM); in IR_TX_adp_Init()38 UADP_SPT_0NXT(IRTX_SETCARRIERCOUNT_PARAM); in IR_TX_adp_Init()39 UADP_SPT_0NXT(IRTX_INIT_PARAM); in IR_TX_adp_Init()
37 UADP_SPT_0NXT(GPIO_Status); in GPIO_adp_Init()38 UADP_SPT_0NXT(GPIO_SET_HIGH_PARAM); in GPIO_adp_Init()39 UADP_SPT_0NXT(GPIO_SET_LOW_PARAM); in GPIO_adp_Init()40 UADP_SPT_0NXT(GPIO_SET_INPUT_PARAM); in GPIO_adp_Init()41 UADP_SPT_0NXT(GPIO_GET_INOUT_PARAM); in GPIO_adp_Init()42 UADP_SPT_0NXT(GPIO_GET_LEVEL_PARAM); in GPIO_adp_Init()43 UADP_SPT_0NXT(GPIO_DETACH_INTERRUPT_PARAM); in GPIO_adp_Init()44 UADP_SPT_0NXT(GPIO_ENABLE_INTERRUPT_PARAM); in GPIO_adp_Init()45 UADP_SPT_0NXT(GPIO_DISABLE_INTERRUPT_PARAM); in GPIO_adp_Init()47 UADP_SPT_0NXT(GPIO_DISABLE_INTERRUPT_PARAM); in GPIO_adp_Init()
30 UADP_SPT_0NXT(SEM_GETRESOURCE_PARAM); in SEM_adp_Init()31 UADP_SPT_0NXT(SEM_FREERESOURCE_PARAM); in SEM_adp_Init()32 UADP_SPT_0NXT(SEM_RESETRESOURCE_PARAM); in SEM_adp_Init()33 UADP_SPT_0NXT(SEM_GETRESOURCEID_PARAM); in SEM_adp_Init()34 UADP_SPT_0NXT(SEM_GETLIBVER_PARAM); in SEM_adp_Init()35 UADP_SPT_0NXT(SEM_LOCK_PARAM); in SEM_adp_Init()36 UADP_SPT_0NXT(SEM_UNLOCK_PARAM); in SEM_adp_Init()37 UADP_SPT_0NXT(SEM_DELETE_PARAM); in SEM_adp_Init()
116 UADP_SPT_0NXT(HWI2C_UnitCfg); in HWI2C_adp_Init()118 UADP_SPT_0NXT(HWI2C_PRIVATE_PARAM_SelectPort); in HWI2C_adp_Init()119 UADP_SPT_0NXT(HWI2C_PRIVATE_PARAM_SetClk); in HWI2C_adp_Init()
814 UADP_SPT_0NXT(MS_U8); in utopia_init()815 UADP_SPT_0NXT(MS_U16); in utopia_init()816 UADP_SPT_0NXT(MS_U32); in utopia_init()817 UADP_SPT_0NXT(MS_NULL); in utopia_init()
34 UADP_SPT_0NXT(SAR_PRIVATE_PARAM_Kpd_GetKeyCode); in SAR_adp_Init()35 UADP_SPT_0NXT(SAR_KpdRegCfg); in SAR_adp_Init()
55 UADP_SPT_0NXT(BDMA_CRC32_PARAM); in BDMA_adp_Init()56 UADP_SPT_0NXT(BDMA_MEMCOPY_PARAM); in BDMA_adp_Init()
233 #define UADP_SPT_0NXT(TYPE) UADP_SP… macro