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/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A Dk6_SC1_Main.c29 code U8 MST_SkipRule_IP_SC1_Main[PQ_IP_NUM_SC1_Main]=
83 code U8 MST_AFEC_COM_SC1_Main[][4] =
88 code U8 MST_AFEC_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_SC1_Main]=
96 code U8 MST_Comb_COM_SC1_Main[][4] =
101 code U8 MST_Comb_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_SC1_Main]=
109 code U8 MST_Comb2_COM_SC1_Main[][4] =
114 code U8 MST_Comb2_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb2_NUMS_SC1_Main]=
122 code U8 MST_SECAM_COM_SC1_Main[][4] =
127 code U8 MST_SECAM_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_SC1_Main]=
135 code U8 MST_VD_Sampling_no_comm_COM_SC1_Main[][4] =
[all …]
H A Dk6_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
56 code U8 MST_AFEC_COM_Sub[][4] =
61 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
69 code U8 MST_Comb_COM_Sub[][4] =
74 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
82 code U8 MST_SECAM_COM_Sub[][4] =
87 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
95 code U8 MST_SCinit_COM_Sub[][4] =
109 code U8 MST_SCinit_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Sub]=
117 code U8 MST_CSC_COM_Sub[][4] =
[all …]
H A Dk6_Main.c29 code U8 MST_SkipRule_IP_Main[PQ_IP_NUM_Main]=
56 code U8 MST_AFEC_COM_Main[][4] =
61 code U8 MST_AFEC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Main]=
69 code U8 MST_Comb_COM_Main[][4] =
74 code U8 MST_Comb_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Main]=
82 code U8 MST_SECAM_COM_Main[][4] =
87 code U8 MST_SECAM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Main]=
95 code U8 MST_SCinit_COM_Main[][4] =
110 code U8 MST_SCinit_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Main]=
118 code U8 MST_CSC_COM_Main[][4] =
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DKano_SC1_Main.c29 code U8 MST_SkipRule_IP_SC1_Main[PQ_IP_NUM_SC1_Main]=
83 code U8 MST_AFEC_COM_SC1_Main[][4] =
93 code U8 MST_AFEC_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_SC1_Main]=
104 code U8 MST_Comb_COM_SC1_Main[][4] =
199 code U8 MST_Comb_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_SC1_Main]=
1007 code U8 MST_Comb2_COM_SC1_Main[][4] =
1022 code U8 MST_Comb2_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb2_NUMS_SC1_Main]=
1062 code U8 MST_SECAM_COM_SC1_Main[][4] =
1102 code U8 MST_SECAM_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_SC1_Main]=
1110 code U8 MST_VD_Sampling_no_comm_COM_SC1_Main[][4] =
[all …]
H A DKano_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
56 code U8 MST_AFEC_COM_Sub[][4] =
61 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
69 code U8 MST_Comb_COM_Sub[][4] =
74 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
82 code U8 MST_SECAM_COM_Sub[][4] =
87 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
95 code U8 MST_SCinit_COM_Sub[][4] =
109 code U8 MST_SCinit_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Sub]=
117 code U8 MST_CSC_COM_Sub[][4] =
[all …]
H A DKano_Main.c29 code U8 MST_SkipRule_IP_Main[PQ_IP_NUM_Main]=
56 code U8 MST_AFEC_COM_Main[][4] =
61 code U8 MST_AFEC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Main]=
69 code U8 MST_Comb_COM_Main[][4] =
74 code U8 MST_Comb_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Main]=
82 code U8 MST_SECAM_COM_Main[][4] =
87 code U8 MST_SECAM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Main]=
95 code U8 MST_SCinit_COM_Main[][4] =
110 code U8 MST_SCinit_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Main]=
118 code U8 MST_CSC_COM_Main[][4] =
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DCurry_SC1_Main.c29 code U8 MST_SkipRule_IP_SC1_Main[PQ_IP_NUM_SC1_Main]=
83 code U8 MST_AFEC_COM_SC1_Main[][4] =
93 code U8 MST_AFEC_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_SC1_Main]=
104 code U8 MST_Comb_COM_SC1_Main[][4] =
199 code U8 MST_Comb_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_SC1_Main]=
1007 code U8 MST_Comb2_COM_SC1_Main[][4] =
1022 code U8 MST_Comb2_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb2_NUMS_SC1_Main]=
1062 code U8 MST_SECAM_COM_SC1_Main[][4] =
1102 code U8 MST_SECAM_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_SC1_Main]=
1110 code U8 MST_VD_Sampling_no_comm_COM_SC1_Main[][4] =
[all …]
H A DKano_SC1_Main.c29 code U8 MST_SkipRule_IP_SC1_Main[PQ_IP_NUM_SC1_Main]=
83 code U8 MST_AFEC_COM_SC1_Main[][4] =
93 code U8 MST_AFEC_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_SC1_Main]=
104 code U8 MST_Comb_COM_SC1_Main[][4] =
199 code U8 MST_Comb_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_SC1_Main]=
1007 code U8 MST_Comb2_COM_SC1_Main[][4] =
1022 code U8 MST_Comb2_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb2_NUMS_SC1_Main]=
1062 code U8 MST_SECAM_COM_SC1_Main[][4] =
1102 code U8 MST_SECAM_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_SC1_Main]=
1110 code U8 MST_VD_Sampling_no_comm_COM_SC1_Main[][4] =
[all …]
H A DCurry_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
56 code U8 MST_AFEC_COM_Sub[][4] =
61 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
69 code U8 MST_Comb_COM_Sub[][4] =
74 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
82 code U8 MST_SECAM_COM_Sub[][4] =
87 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
95 code U8 MST_SCinit_COM_Sub[][4] =
109 code U8 MST_SCinit_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Sub]=
117 code U8 MST_CSC_COM_Sub[][4] =
[all …]
H A DKano_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
56 code U8 MST_AFEC_COM_Sub[][4] =
61 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
69 code U8 MST_Comb_COM_Sub[][4] =
74 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
82 code U8 MST_SECAM_COM_Sub[][4] =
87 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
95 code U8 MST_SCinit_COM_Sub[][4] =
109 code U8 MST_SCinit_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Sub]=
117 code U8 MST_CSC_COM_Sub[][4] =
[all …]
H A DCurry_Main.c29 code U8 MST_SkipRule_IP_Main[PQ_IP_NUM_Main]=
56 code U8 MST_AFEC_COM_Main[][4] =
61 code U8 MST_AFEC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Main]=
69 code U8 MST_Comb_COM_Main[][4] =
74 code U8 MST_Comb_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Main]=
82 code U8 MST_SECAM_COM_Main[][4] =
87 code U8 MST_SECAM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Main]=
95 code U8 MST_SCinit_COM_Main[][4] =
110 code U8 MST_SCinit_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Main]=
118 code U8 MST_CSC_COM_Main[][4] =
[all …]
H A DKano_Main.c29 code U8 MST_SkipRule_IP_Main[PQ_IP_NUM_Main]=
56 code U8 MST_AFEC_COM_Main[][4] =
61 code U8 MST_AFEC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Main]=
69 code U8 MST_Comb_COM_Main[][4] =
74 code U8 MST_Comb_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Main]=
82 code U8 MST_SECAM_COM_Main[][4] =
87 code U8 MST_SECAM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Main]=
95 code U8 MST_SCinit_COM_Main[][4] =
110 code U8 MST_SCinit_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Main]=
118 code U8 MST_CSC_COM_Main[][4] =
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
87 code U8 MST_AFEC_COM_Sub[][4] =
97 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
108 code U8 MST_Comb_COM_Sub[][4] =
281 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
1696 code U8 MST_SECAM_COM_Sub[][4] =
1736 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
1744 code U8 MST_VD_Sampling_no_comm_COM_Sub[][4] =
1749 code U8 MST_VD_Sampling_no_comm_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VD_Sampling_no_comm_NUMS_Su…
1967 code U8 MST_ADC_Sampling_COM_Sub[][4] =
[all …]
H A DMaxim_Main_GRule.h359 extern code U8 MST_GRule_NR_IP_Index_Main[PQ_GRULE_NR_IP_NUM_Main];
360 extern code U8 MST_GRule_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_NR_NUM_Main][PQ_GRULE_NR_IP_NUM_Ma…
364 extern code U8 MST_GRule_OSD_BW_IP_Index_Main[PQ_GRULE_OSD_BW_IP_NUM_Main];
365 extern code U8 MST_GRule_OSD_BW_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_OSD_BW_NUM_Main][PQ_GRULE_OSD_…
369 extern code U8 MST_GRule_MPEG_NR_IP_Index_Main[PQ_GRULE_MPEG_NR_IP_NUM_Main];
370 extern code U8 MST_GRule_MPEG_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_MPEG_NR_NUM_Main][PQ_GRULE_MP…
374 extern code U8 MST_GRule_FILM_MODE_IP_Index_Main[PQ_GRULE_FILM_MODE_IP_NUM_Main];
375 extern code U8 MST_GRule_FILM_MODE_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_FILM_MODE_NUM_Main][PQ_GRUL…
379 extern code U8 MST_GRule_ULTRAT_CLEAR_IP_Index_Main[PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main];
380 extern code U8 MST_GRule_ULTRAT_CLEAR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_ULTRAT_CLEAR_NUM_Main][P…
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DMaxim_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
87 code U8 MST_AFEC_COM_Sub[][4] =
97 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
108 code U8 MST_Comb_COM_Sub[][4] =
281 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
1696 code U8 MST_SECAM_COM_Sub[][4] =
1736 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
1744 code U8 MST_VD_Sampling_no_comm_COM_Sub[][4] =
1749 code U8 MST_VD_Sampling_no_comm_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VD_Sampling_no_comm_NUMS_Su…
1967 code U8 MST_ADC_Sampling_COM_Sub[][4] =
[all …]
H A DMaxim_Main_GRule.h359 extern code U8 MST_GRule_NR_IP_Index_Main[PQ_GRULE_NR_IP_NUM_Main];
360 extern code U8 MST_GRule_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_NR_NUM_Main][PQ_GRULE_NR_IP_NUM_Ma…
364 extern code U8 MST_GRule_OSD_BW_IP_Index_Main[PQ_GRULE_OSD_BW_IP_NUM_Main];
365 extern code U8 MST_GRule_OSD_BW_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_OSD_BW_NUM_Main][PQ_GRULE_OSD_…
369 extern code U8 MST_GRule_MPEG_NR_IP_Index_Main[PQ_GRULE_MPEG_NR_IP_NUM_Main];
370 extern code U8 MST_GRule_MPEG_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_MPEG_NR_NUM_Main][PQ_GRULE_MP…
374 extern code U8 MST_GRule_FILM_MODE_IP_Index_Main[PQ_GRULE_FILM_MODE_IP_NUM_Main];
375 extern code U8 MST_GRule_FILM_MODE_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_FILM_MODE_NUM_Main][PQ_GRUL…
379 extern code U8 MST_GRule_ULTRAT_CLEAR_IP_Index_Main[PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main];
380 extern code U8 MST_GRule_ULTRAT_CLEAR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_ULTRAT_CLEAR_NUM_Main][P…
[all …]
/utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/include/
H A DdrvUSB.h99 U8 MDrv_USBGetPortEnableStatus(void);
103 extern BOOLEAN MDrv_UsbBlockReadToMIU_Port2(U8 lun,U32 u32BlockAddr, U32 u32BlockNum,U32 u32Buffer);
104 extern BOOLEAN MDrv_UsbBlockWriteFromMIU_Port2(U8 lun,U32 u32BlockAddr, U32 u32BlockNum,U32 u32Buff…
106 U8 MDrv_GET_MASS_MAX_LUN_PORT2(void);
107 U8 MDrv_GET_MASS_VALID_LUN_PORT2(void);
109 extern U8 MDrv_Usb_Device_Enum_EX_Port2(void);
112 extern U8 MDrv_UsbGetMaxLUNCount_Port2(void);
114 U32 MDrv_GetUsbBlockSize_Port2(U8 lun);
115 U32 MDrv_GetUsbBlockNum_Port2(U8 lun);
117 U8 MDrv_GetUsbDeviceStatusPort2(void);
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
74 code U8 MST_AFEC_COM_Sub[][4] =
84 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
95 code U8 MST_Comb_COM_Sub[][4] =
268 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
1683 code U8 MST_SECAM_COM_Sub[][4] =
1723 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
1731 code U8 MST_VD_Sampling_no_comm_COM_Sub[][4] =
1736 code U8 MST_VD_Sampling_no_comm_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VD_Sampling_no_comm_NUMS_Su…
1954 code U8 MST_ADC_Sampling_COM_Sub[][4] =
[all …]
H A DMaserati_Main_GRule.h361 extern code U8 MST_GRule_NR_IP_Index_Main[PQ_GRULE_NR_IP_NUM_Main];
362 extern code U8 MST_GRule_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_NR_NUM_Main][PQ_GRULE_NR_IP_NUM_Ma…
366 extern code U8 MST_GRule_OSD_BW_IP_Index_Main[PQ_GRULE_OSD_BW_IP_NUM_Main];
367 extern code U8 MST_GRule_OSD_BW_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_OSD_BW_NUM_Main][PQ_GRULE_OSD_…
371 extern code U8 MST_GRule_MPEG_NR_IP_Index_Main[PQ_GRULE_MPEG_NR_IP_NUM_Main];
372 extern code U8 MST_GRule_MPEG_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_MPEG_NR_NUM_Main][PQ_GRULE_MP…
376 extern code U8 MST_GRule_FILM_MODE_IP_Index_Main[PQ_GRULE_FILM_MODE_IP_NUM_Main];
377 extern code U8 MST_GRule_FILM_MODE_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_FILM_MODE_NUM_Main][PQ_GRUL…
381 extern code U8 MST_GRule_ULTRAT_CLEAR_IP_Index_Main[PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main];
382 extern code U8 MST_GRule_ULTRAT_CLEAR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_ULTRAT_CLEAR_NUM_Main][P…
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
74 code U8 MST_AFEC_COM_Sub[][4] =
84 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
95 code U8 MST_Comb_COM_Sub[][4] =
268 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
1683 code U8 MST_SECAM_COM_Sub[][4] =
1723 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
1731 code U8 MST_VD_Sampling_no_comm_COM_Sub[][4] =
1736 code U8 MST_VD_Sampling_no_comm_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VD_Sampling_no_comm_NUMS_Su…
1954 code U8 MST_ADC_Sampling_COM_Sub[][4] =
[all …]
H A DMaserati_Main_GRule.h361 extern code U8 MST_GRule_NR_IP_Index_Main[PQ_GRULE_NR_IP_NUM_Main];
362 extern code U8 MST_GRule_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_NR_NUM_Main][PQ_GRULE_NR_IP_NUM_Ma…
366 extern code U8 MST_GRule_OSD_BW_IP_Index_Main[PQ_GRULE_OSD_BW_IP_NUM_Main];
367 extern code U8 MST_GRule_OSD_BW_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_OSD_BW_NUM_Main][PQ_GRULE_OSD_…
371 extern code U8 MST_GRule_MPEG_NR_IP_Index_Main[PQ_GRULE_MPEG_NR_IP_NUM_Main];
372 extern code U8 MST_GRule_MPEG_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_MPEG_NR_NUM_Main][PQ_GRULE_MP…
376 extern code U8 MST_GRule_FILM_MODE_IP_Index_Main[PQ_GRULE_FILM_MODE_IP_NUM_Main];
377 extern code U8 MST_GRule_FILM_MODE_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_FILM_MODE_NUM_Main][PQ_GRUL…
381 extern code U8 MST_GRule_ULTRAT_CLEAR_IP_Index_Main[PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main];
382 extern code U8 MST_GRule_ULTRAT_CLEAR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_ULTRAT_CLEAR_NUM_Main][P…
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A Dk6lite_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
56 code U8 MST_AFEC_COM_Sub[][4] =
61 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
69 code U8 MST_Comb_COM_Sub[][4] =
74 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
82 code U8 MST_SECAM_COM_Sub[][4] =
87 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
95 code U8 MST_SCinit_COM_Sub[][4] =
109 code U8 MST_SCinit_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Sub]=
117 code U8 MST_CSC_COM_Sub[][4] =
[all …]
H A Dk6lite_Main.c29 code U8 MST_SkipRule_IP_Main[PQ_IP_NUM_Main]=
56 code U8 MST_AFEC_COM_Main[][4] =
61 code U8 MST_AFEC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Main]=
69 code U8 MST_Comb_COM_Main[][4] =
74 code U8 MST_Comb_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Main]=
82 code U8 MST_SECAM_COM_Main[][4] =
87 code U8 MST_SECAM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Main]=
95 code U8 MST_SCinit_COM_Main[][4] =
110 code U8 MST_SCinit_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SCinit_NUMS_Main]=
118 code U8 MST_CSC_COM_Main[][4] =
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main_GRule.h317 extern code U8 MST_GRule_NR_IP_Index_Main[PQ_GRULE_NR_IP_NUM_Main];
318 extern code U8 MST_GRule_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_NR_NUM_Main][PQ_GRULE_NR_IP_NUM_Ma…
322 extern code U8 MST_GRule_OSD_BW_IP_Index_Main[PQ_GRULE_OSD_BW_IP_NUM_Main];
323 extern code U8 MST_GRule_OSD_BW_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_OSD_BW_NUM_Main][PQ_GRULE_OSD_…
327 extern code U8 MST_GRule_MPEG_NR_IP_Index_Main[PQ_GRULE_MPEG_NR_IP_NUM_Main];
328 extern code U8 MST_GRule_MPEG_NR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_MPEG_NR_NUM_Main][PQ_GRULE_MP…
332 extern code U8 MST_GRule_FILM_MODE_IP_Index_Main[PQ_GRULE_FILM_MODE_IP_NUM_Main];
333 extern code U8 MST_GRule_FILM_MODE_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_FILM_MODE_NUM_Main][PQ_GRUL…
337 extern code U8 MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main];
338 extern code U8 MST_GRule_DYNAMIC_CONTRAST_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_NUM…
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H A DManhattan_Sub.c29 code U8 MST_SkipRule_IP_Sub[PQ_IP_NUM_Sub]=
88 code U8 MST_AFEC_COM_Sub[][4] =
98 code U8 MST_AFEC_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_NUMS_Sub]=
109 code U8 MST_Comb_COM_Sub[][4] =
282 code U8 MST_Comb_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Comb_NUMS_Sub]=
1739 code U8 MST_SECAM_COM_Sub[][4] =
1779 code U8 MST_SECAM_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SECAM_NUMS_Sub]=
1787 code U8 MST_VD_Sampling_no_comm_COM_Sub[][4] =
1792 code U8 MST_VD_Sampling_no_comm_Sub[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VD_Sampling_no_comm_NUMS_Su…
2010 code U8 MST_ADC_Sampling_COM_Sub[][4] =
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