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Searched refs:REG_TC_VE_ENC2_BASE (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/
H A Dmdrv_macrovision_tbl.h120 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
742 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
744 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
745 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
746 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
747 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
748 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
749 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
750 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h124 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
843 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
845 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
846 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
847 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
848 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
849 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
850 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
851 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/
H A Dmdrv_macrovision_tbl.h120 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
742 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
744 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
745 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
746 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
747 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
748 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
749 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
750 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h124 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
843 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
845 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
846 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
847 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
848 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
849 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
850 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
851 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/
H A Dmdrv_macrovision_tbl.h120 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
742 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
744 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
745 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
746 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
747 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
748 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
749 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
750 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h124 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
843 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
845 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
846 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
847 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
848 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
849 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
850 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
851 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/
H A Dmdrv_macrovision_tbl.h120 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
742 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
744 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
745 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
746 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
747 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
748 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
749 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
750 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h124 #define REG_TC_VE_ENC2_BASE 0x3F00 macro
843 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00)
844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01)
845 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02)
846 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03)
847 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04)
848 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05)
849 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06)
850 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07)
851 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08)
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