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Searched refs:REG_TC_VE_ENC1_BASE (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/
H A Dmdrv_macrovision_tbl.h119 #define REG_TC_VE_ENC1_BASE 0x3E00 macro
485 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
486 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
487 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
488 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
489 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
490 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
491 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
492 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
493 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h585 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
586 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
587 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
588 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
589 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
590 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
591 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
592 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
593 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
594 #define REG_TC_VE_ENC1_04_H (REG_TC_VE_ENC1_BASE + 0x09)
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/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/
H A Dmdrv_macrovision_tbl.h119 #define REG_TC_VE_ENC1_BASE 0x3E00 macro
485 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
486 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
487 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
488 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
489 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
490 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
491 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
492 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
493 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h585 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
586 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
587 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
588 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
589 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
590 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
591 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
592 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
593 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
594 #define REG_TC_VE_ENC1_04_H (REG_TC_VE_ENC1_BASE + 0x09)
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/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/
H A Dmdrv_macrovision_tbl.h119 #define REG_TC_VE_ENC1_BASE 0x3E00 macro
485 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
486 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
487 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
488 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
489 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
490 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
491 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
492 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
493 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h585 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
586 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
587 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
588 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
589 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
590 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
591 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
592 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
593 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
594 #define REG_TC_VE_ENC1_04_H (REG_TC_VE_ENC1_BASE + 0x09)
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/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/
H A Dmdrv_macrovision_tbl.h119 #define REG_TC_VE_ENC1_BASE 0x3E00 macro
485 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
486 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
487 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
488 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
489 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
490 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
491 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
492 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
493 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
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H A Dmdrv_dcs_tbl.h585 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00)
586 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01)
587 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02)
588 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03)
589 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04)
590 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05)
591 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06)
592 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07)
593 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08)
594 #define REG_TC_VE_ENC1_04_H (REG_TC_VE_ENC1_BASE + 0x09)
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