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Searched refs:REG_TC_LPLL_31_H (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c9191 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9192 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9193 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9194 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9196 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9739 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9740 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9741 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9742 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9744 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c9088 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9089 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9090 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9091 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9093 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9630 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9631 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9632 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9633 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9635 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c9190 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9191 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9192 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9193 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9195 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9738 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9739 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9740 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9741 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9743 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c8757 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
8758 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
8759 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
8760 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
8762 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9282 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9283 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9284 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9285 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9287 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c8757 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
8758 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
8759 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
8760 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
8762 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9282 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9283 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9284 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9285 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9287 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c9088 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9089 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9090 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9091 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9093 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9630 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9631 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9632 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9633 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9635 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c8757 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
8758 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
8759 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
8760 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
8762 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9282 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9283 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9284 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9285 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9287 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c8757 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
8758 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
8759 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
8760 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
8762 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
9282 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x80, 0x00/*ALL*/, },
9283 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x10, 0x10/*ALL*/, },
9284 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x20, 0x20/*ALL*/, },
9285 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x40, 0x00/*ALL*/, },
9287 { DRV_DAC_REG(REG_TC_LPLL_31_H), 0x0F, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
H A Dmdrv_dac_tbl.h1359 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A Dpnl_tcon_tbl.h1239 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A Dpnl_tcon_tbl.h1239 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A Dpnl_tcon_tbl.h1239 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
H A Dmdrv_dac_tbl.h1359 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A Dpnl_tcon_tbl.h1239 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dpnl_tcon_tbl.h1241 #define REG_TC_LPLL_31_H (REG_TC_LPLL_BASE + 0x63) macro

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