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Searched refs:REG_TC_LPLL_10_L (Results 1 – 25 of 38) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c9175 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9723 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10271 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10819 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11367 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11915 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12461 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13007 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13553 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
14099 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c9072 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9614 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10156 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10698 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11240 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11782 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12322 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12862 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13402 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13942 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c9174 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9722 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10270 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10818 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11366 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11914 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12460 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13006 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13552 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
14098 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c8741 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9266 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9791 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10316 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10841 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11366 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11891 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12416 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12941 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13466 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c8741 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9266 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9791 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10316 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10841 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11366 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11891 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12416 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12941 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13466 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c9072 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9614 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10156 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10698 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11240 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11782 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12322 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12862 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13402 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13942 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c8741 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9266 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9791 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10316 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10841 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11366 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11891 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12416 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12941 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13466 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c8741 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9266 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
9791 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10316 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
10841 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11366 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
11891 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12416 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
12941 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
13466 { DRV_DAC_REG(REG_TC_LPLL_10_L), 0xFF, 0x99/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
H A Dmdrv_dac_tbl.h1292 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A Dpnl_tcon_tbl.h1172 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A Dpnl_tcon_tbl.h1172 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A Dpnl_tcon_tbl.h1172 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
H A Dmdrv_dac_tbl.h1292 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A Dpnl_tcon_tbl.h1172 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dpnl_tcon_tbl.h1174 #define REG_TC_LPLL_10_L (REG_TC_LPLL_BASE + 0x20) macro

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