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Searched refs:REG_TC_LPLL_00_L (Results 1 – 25 of 38) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c9199 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9747 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10295 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10843 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11391 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11939 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12485 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13031 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13577 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
14123 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c9096 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10180 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10722 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11264 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11806 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12346 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12886 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13426 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13966 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c9198 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9746 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10294 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10842 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11390 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11938 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12484 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13030 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13576 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
14122 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c8765 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9290 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9815 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10340 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10865 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11390 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11915 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12440 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12965 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13490 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c8765 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9290 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9815 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10340 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10865 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11390 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11915 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12440 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12965 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13490 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c9096 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10180 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10722 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11264 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11806 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12346 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12886 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13426 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13966 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c8765 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9290 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9815 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10340 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10865 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11390 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11915 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12440 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12965 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13490 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c8765 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9290 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
9815 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10340 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
10865 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11390 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
11915 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12440 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
12965 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
13490 { DRV_DAC_REG(REG_TC_LPLL_00_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
H A Dmdrv_dac_tbl.h1260 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A Dpnl_tcon_tbl.h1140 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A Dpnl_tcon_tbl.h1140 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A Dpnl_tcon_tbl.h1140 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
H A Dmdrv_dac_tbl.h1260 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A Dpnl_tcon_tbl.h1140 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dpnl_tcon_tbl.h1142 #define REG_TC_LPLL_00_L (REG_TC_LPLL_BASE + 0x00) macro

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