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Searched refs:REG_TC_HDMITX_PLL_34_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c9537 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9565 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9593 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9621 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10633 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10661 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c9428 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9456 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9484 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9970 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9998 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10026 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10054 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10540 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c9536 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9564 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9592 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9620 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10084 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10112 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10140 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10168 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10632 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10660 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c9084 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9112 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9140 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9168 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9609 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9637 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9665 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9693 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10134 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10162 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7359 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c9084 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9112 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9140 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9168 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9609 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9637 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9665 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9693 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10134 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10162 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7359 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c9428 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9456 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9484 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9970 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9998 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10026 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10054 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10540 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c9084 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9112 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9140 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9168 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9609 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9637 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9665 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9693 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10134 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10162 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7359 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c9084 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9112 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9140 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9168 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9609 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9637 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9665 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
9693 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10134 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
10162 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_L), 0xFF, 0x40/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7359 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3420 #define REG_TC_HDMITX_PLL_34_L (REG_TC_HDMITX_PLL_BASE + 0x68) macro