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Searched refs:REG_TC_HDMITX_PLL_34_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c9538 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9566 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9594 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9622 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10086 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10114 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10142 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10170 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10634 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10662 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c9429 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9485 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9971 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9999 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10027 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10055 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10541 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c9537 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9565 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9593 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9621 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10633 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10661 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c9085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9610 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9666 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9694 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10135 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10163 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7360 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c9085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9610 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9666 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9694 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10135 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10163 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7360 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c9429 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9485 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9971 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9999 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10027 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10055 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10541 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c9085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9610 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9666 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9694 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10135 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10163 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7360 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c9085 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9113 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9141 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9169 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9610 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9638 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9666 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
9694 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10135 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
10163 { DRV_DAC_REG(REG_TC_HDMITX_PLL_34_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7360 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3421 #define REG_TC_HDMITX_PLL_34_H (REG_TC_HDMITX_PLL_BASE + 0x69) macro