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Searched refs:REG_TC_HDMITX_PLL_11_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c447 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
480 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
546 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
978 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1011 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1044 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1077 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1546 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c441 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
474 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
507 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
540 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
966 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
999 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1032 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1065 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1495 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1528 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c447 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
480 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
546 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
978 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1011 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1044 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1077 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1513 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1546 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c426 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
459 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
492 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
525 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
936 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
969 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1002 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1035 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1450 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1483 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7289 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c426 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
459 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
492 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
525 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
936 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
969 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1002 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1035 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1450 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1483 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7289 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c441 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
474 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
507 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
540 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
966 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
999 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1032 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1065 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1495 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1528 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c426 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
459 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
492 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
525 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
936 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
969 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1002 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1035 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1450 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1483 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7289 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c426 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
459 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
492 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
525 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
936 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
969 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
1002 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x00/*ALL*/, },
1035 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1450 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x99/*ALL*/, },
1483 { DRV_DAC_REG(REG_TC_HDMITX_PLL_11_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7289 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3350 #define REG_TC_HDMITX_PLL_11_L (REG_TC_HDMITX_PLL_BASE + 0x22) macro