Home
last modified time | relevance | path

Searched refs:REG_TC_HDMITX_PLL_10_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c445 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
478 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
511 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
544 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
976 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1009 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1042 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1075 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1511 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1544 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c439 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
472 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
505 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
538 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
964 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
997 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1030 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1063 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1493 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1526 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c445 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
478 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
511 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
544 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
976 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1009 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1042 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1075 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1511 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1544 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c424 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
490 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
523 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
934 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
967 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1000 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1033 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1448 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1481 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7287 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c424 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
490 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
523 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
934 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
967 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1000 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1033 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1448 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1481 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7287 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c439 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
472 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
505 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
538 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
964 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
997 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1030 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1063 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1493 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1526 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c424 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
490 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
523 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
934 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
967 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1000 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1033 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1448 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1481 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7287 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c424 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
457 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
490 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
523 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
934 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
967 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
1000 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x00/*ALL*/, },
1033 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1448 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x99/*ALL*/, },
1481 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_L), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7287 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3348 #define REG_TC_HDMITX_PLL_10_L (REG_TC_HDMITX_PLL_BASE + 0x20) macro