Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_64_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c413 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1479 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2541 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3607 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4142 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4673 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5205 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1459 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1984 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2509 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3034 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3563 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4092 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4617 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5142 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c413 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1479 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2541 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3607 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4142 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4673 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5204 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1432 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1942 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2452 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3476 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4500 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6941 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1432 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1942 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2452 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3476 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4500 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6941 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1459 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1984 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2509 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3034 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3563 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4092 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4617 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5142 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1432 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1942 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2452 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3476 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4500 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6941 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1432 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
1942 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
2452 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3476 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x5c/*ALL*/, },
4500 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
5010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_64_L), 0xFF, 0x50/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6941 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3259 #define REG_TC_HDGEN_BK1_64_L _PK_L_(0x1, 0x64) macro