Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_49_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c359 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1425 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2487 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3018 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3553 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4088 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4619 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
5151 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c351 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2455 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2980 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3509 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4038 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4563 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
5088 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c359 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1425 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2487 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3018 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3553 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4088 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4619 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
5150 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1378 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3422 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3936 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
4956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6887 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1378 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3422 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3936 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
4956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6887 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c351 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2455 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2980 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3509 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4038 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4563 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
5088 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1378 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3422 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3936 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
4956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6887 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1378 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
1888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x49/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
2908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3422 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
3936 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x0b/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
4956 { DRV_DAC_REG(REG_TC_HDGEN_BK1_49_L), 0xFF, 0x33/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6887 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3205 #define REG_TC_HDGEN_BK1_49_L _PK_L_(0x1, 0x49) macro