Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_47_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c355 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2483 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3014 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3549 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4084 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4615 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
5147 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1401 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1926 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2451 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2976 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3505 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4034 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4559 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
5084 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c355 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2483 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3014 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3549 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4084 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4615 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
5146 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3418 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
4952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6883 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3418 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
4952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6883 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1401 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1926 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2451 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2976 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3505 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4034 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4559 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
5084 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3418 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
4952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6883 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
1884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x28/*ALL*/, },
2394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
2904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3418 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
3932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x00/*ALL*/, },
4442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
4952 { DRV_DAC_REG(REG_TC_HDGEN_BK1_47_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6883 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3201 #define REG_TC_HDGEN_BK1_47_L _PK_L_(0x1, 0x47) macro