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Searched refs:REG_TC_HDGEN_BK1_46_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1419 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2481 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3012 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3547 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4082 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4613 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
5145 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c345 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1399 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2449 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2974 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3503 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4032 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4557 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
5082 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1419 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2481 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3012 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3547 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4082 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4613 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
5144 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c348 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1372 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2902 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3416 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
4950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6881 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c348 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1372 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2902 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3416 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
4950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6881 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c345 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1399 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2449 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2974 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3503 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4032 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4557 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
5082 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c348 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1372 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2902 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3416 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
4950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6881 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c348 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1372 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x1a/*ALL*/, },
2392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
2902 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3416 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
3930 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x00/*ALL*/, },
4440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
4950 { DRV_DAC_REG(REG_TC_HDGEN_BK1_46_L), 0xFF, 0x39/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6881 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3199 #define REG_TC_HDGEN_BK1_46_L _PK_L_(0x1, 0x46) macro