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Searched refs:REG_TC_HDGEN_BK1_45_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c351 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1417 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2479 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3545 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4080 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4611 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
5143 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c343 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1922 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2447 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2972 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3501 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4030 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4555 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
5080 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c351 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1417 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2479 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3010 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3545 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4080 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4611 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
5142 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2900 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
4948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6879 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2900 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
4948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6879 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c343 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1922 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2447 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2972 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3501 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4030 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4555 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
5080 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2900 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
4948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6879 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
1880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x20/*ALL*/, },
2390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
2900 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
3928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x00/*ALL*/, },
4438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
4948 { DRV_DAC_REG(REG_TC_HDGEN_BK1_45_L), 0xFF, 0x06/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6879 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3197 #define REG_TC_HDGEN_BK1_45_L _PK_L_(0x1, 0x45) macro