Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_42_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
877 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1412 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2474 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3005 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3540 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4075 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4606 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
5138 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1917 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
2967 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
3496 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4025 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4550 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
5075 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
877 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1412 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2474 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3005 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3540 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4075 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4606 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
5137 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3923 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4433 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6874 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3923 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4433 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6874 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1917 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2442 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
2967 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
3496 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4025 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4550 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
5075 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3923 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4433 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6874 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
1875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
2895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
3923 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4433 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
4943 { DRV_DAC_REG(REG_TC_HDGEN_BK1_42_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6874 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3192 #define REG_TC_HDGEN_BK1_42_H _PK_H_(0x1, 0x42) macro