Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_41_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c344 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2472 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3003 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3538 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4073 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4604 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
5136 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
861 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
2965 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
3494 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4023 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4548 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
5073 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c344 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
875 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2472 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3003 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3538 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4073 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4604 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
5135 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1363 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2383 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2893 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4431 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6872 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1363 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2383 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2893 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4431 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6872 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
861 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1390 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2440 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
2965 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
3494 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4023 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4548 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
5073 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1363 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2383 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2893 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4431 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6872 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1363 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
1873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2383 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
2893 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4431 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
4941 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_H), 0xFF, 0x04/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6872 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3190 #define REG_TC_HDGEN_BK1_41_H _PK_H_(0x1, 0x41) macro