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Searched refs:REG_TC_HDGEN_BK1_40_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2469 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3000 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3535 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4070 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4601 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
5133 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1387 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1912 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2437 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3491 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4020 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4545 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
5070 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c341 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2469 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3000 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3535 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4070 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4601 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
5132 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
846 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1360 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4428 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
4938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6869 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
846 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1360 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4428 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
4938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6869 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
858 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1387 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1912 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2437 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2962 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3491 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4020 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4545 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
5070 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
846 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1360 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4428 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
4938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6869 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
846 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1360 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
1870 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x03/*ALL*/, },
2380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
2890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
3918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x00/*ALL*/, },
4428 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
4938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_L), 0xFF, 0x0a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6869 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3187 #define REG_TC_HDGEN_BK1_40_L _PK_L_(0x1, 0x40) macro