Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_40_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2470 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3001 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3536 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4071 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4602 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
5134 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c334 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
859 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1388 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1913 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2963 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3492 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4021 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4546 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
5071 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
873 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1408 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2470 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3001 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3536 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4071 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4602 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
5133 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1361 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1871 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3919 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4429 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6870 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1361 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1871 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3919 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4429 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6870 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c334 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
859 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1388 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1913 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2438 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2963 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3492 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4021 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4546 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
5071 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1361 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1871 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3919 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4429 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6870 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1361 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
1871 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
3919 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4429 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
4939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_40_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6870 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3188 #define REG_TC_HDGEN_BK1_40_H _PK_H_(0x1, 0x40) macro