Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_36_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c319 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
850 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2447 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2978 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3513 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4048 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4579 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
5111 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c311 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2415 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3469 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3998 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4523 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
5048 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c319 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
850 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1385 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2447 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2978 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3513 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4048 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4579 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
5110 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c314 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2358 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6849 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c314 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2358 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6849 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c311 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1365 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1890 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2415 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3469 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3998 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4523 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
5048 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c314 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2358 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6849 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c314 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3e/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x74/*ALL*/, },
1338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x2b/*ALL*/, },
1848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x4f/*ALL*/, },
2358 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
2868 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x38/*ALL*/, },
3382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
3896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
4916 { DRV_DAC_REG(REG_TC_HDGEN_BK1_36_L), 0xFF, 0x3d/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6849 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3167 #define REG_TC_HDGEN_BK1_36_L _PK_L_(0x1, 0x36) macro