Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_35_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c318 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1384 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2977 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3512 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4047 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4578 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
5110 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c310 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
835 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1364 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1889 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3468 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3997 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4522 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
5047 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c318 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
849 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1384 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2977 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3512 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4047 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4578 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
5109 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c313 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
823 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6848 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c313 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
823 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6848 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c310 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
835 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1364 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1889 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2414 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2939 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3468 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3997 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4522 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
5047 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c313 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
823 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6848 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c313 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
823 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1337 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
1847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
2867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3381 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
3895 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4405 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
4915 { DRV_DAC_REG(REG_TC_HDGEN_BK1_35_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6848 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3166 #define REG_TC_HDGEN_BK1_35_H _PK_H_(0x1, 0x35) macro