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Searched refs:REG_TC_HDGEN_BK1_30_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c307 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
838 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2435 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2966 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3501 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4567 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
5099 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c299 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1878 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2403 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3457 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3986 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4511 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
5036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c307 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
838 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2435 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2966 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3501 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4567 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
5098 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c302 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
812 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6837 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c302 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
812 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6837 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c299 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
824 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1878 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2403 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3457 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3986 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4511 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
5036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c302 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
812 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6837 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c302 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
812 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
1836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
2856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
3884 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4394 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
4904 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_L), 0xFF, 0x9a/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6837 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3155 #define REG_TC_HDGEN_BK1_30_L _PK_L_(0x1, 0x30) macro