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Searched refs:REG_TC_HDGEN_BK1_1D_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c270 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
801 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2929 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3464 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3999 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4530 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
5062 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c262 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
787 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1316 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1841 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3949 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4474 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4999 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c270 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
801 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1336 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2929 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3464 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3999 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4530 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
5061 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c265 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
775 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1289 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1799 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2309 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6800 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c265 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
775 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1289 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1799 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2309 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6800 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c262 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
787 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1316 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1841 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2891 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3949 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4474 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4999 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c265 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
775 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1289 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1799 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2309 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6800 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c265 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
775 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1289 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
1799 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2309 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
2819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
3333 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
3847 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x04/*ALL*/, },
4357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
4867 { DRV_DAC_REG(REG_TC_HDGEN_BK1_1D_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6800 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3118 #define REG_TC_HDGEN_BK1_1D_H _PK_H_(0x1, 0x1D) macro