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Searched refs:REG_TC_HDGEN_BK1_18_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c259 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
790 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1325 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2387 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3453 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3988 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4519 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
5051 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c251 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
776 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1830 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2355 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4463 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4988 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c259 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
790 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1325 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2387 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3453 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3988 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4519 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
5050 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c254 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
764 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1278 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1788 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2298 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2808 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3322 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6789 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c254 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
764 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1278 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1788 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2298 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2808 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3322 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6789 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c251 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
776 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1830 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2355 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2880 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3938 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4463 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4988 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c254 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
764 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1278 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1788 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2298 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2808 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3322 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6789 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c254 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
764 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1278 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
1788 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2298 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
2808 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3322 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
3836 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4346 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
4856 { DRV_DAC_REG(REG_TC_HDGEN_BK1_18_L), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6789 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3107 #define REG_TC_HDGEN_BK1_18_L _PK_L_(0x1, 0x18) macro