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Searched refs:REG_SNDR2_CTRL_BASE (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/
H A DregAUDIO.h760 #define REG_SNDR2_CTRL_BASE (REG_R2_1_CTRL_BASE) macro
824 #define REG_SNDR2_CTRL (REG_SNDR2_CTRL_BASE + 0x80)
827 #define REG_SNDR2_ICMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x82)
828 #define REG_SNDR2_ICMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x84)
831 #define REG_SNDR2_ICMEM2_BASE_LO (REG_SNDR2_CTRL_BASE + 0x8C)
832 #define REG_SNDR2_ICMEM2_BASE_HI (REG_SNDR2_CTRL_BASE + 0x8E)
834 #define REG_SNDR2_DCMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x86)
835 #define REG_SNDR2_DCMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x88)
837 #define REG_SNDR2_DQMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x9A)
838 #define REG_SNDR2_DQMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x9C)
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H A DhalAUR2.c263 …HAL_AUR2_WriteMaskByte((REG_SNDR2_CTRL_BASE + 0x40), 0xFF, 0x10); //0x1129_40[5]¬O±±¨îD-side MIUªº… in HAL_SND_R2_EnableR2()
468 tmp_H = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()
469 tmp_L = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()
574 tmp_H = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()
575 tmp_L = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()
/utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/
H A DregAUDIO.h764 #define REG_SNDR2_CTRL_BASE (REG_R2_1_CTRL_BASE) macro
828 #define REG_SNDR2_CTRL (REG_SNDR2_CTRL_BASE + 0x80)
831 #define REG_SNDR2_ICMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x82)
832 #define REG_SNDR2_ICMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x84)
835 #define REG_SNDR2_ICMEM2_BASE_LO (REG_SNDR2_CTRL_BASE + 0x8C)
836 #define REG_SNDR2_ICMEM2_BASE_HI (REG_SNDR2_CTRL_BASE + 0x8E)
838 #define REG_SNDR2_DCMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x86)
839 #define REG_SNDR2_DCMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x88)
841 #define REG_SNDR2_DQMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x9A)
842 #define REG_SNDR2_DQMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x9C)
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H A DhalAUR2.c259 …HAL_AUR2_WriteMaskByte((REG_SNDR2_CTRL_BASE + 0x40), 0xFF, 0x10); //0x1129_40[5]¬O±±¨îD-side MIUªº… in HAL_SND_R2_EnableR2()
438 tmp_H = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()
439 tmp_L = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()
542 tmp_H = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()
543 tmp_L = HAL_AUR2_ReadReg(REG_SNDR2_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()